M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 56

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
3.1 Guide to This Chapter
e
E
v
J
Chapter 3 Functions
This chapter describes the functionality of each instruction by showing syntax, operation, function, select-
able src/dest, flag changes, and description examples.
The following shows how to read this chapter by using an actual page as an example.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
1 .
0
9
0 .
B
0
0
3
1
2
9
0
Chapter 3 Functions
Change
0 -
0
Conditions
Flag
dest
dest
[ Flag Change ]
OR
[ Operation ]
6
[ Selectable src/dest ]
[ Syntax ]
[ Function ]
*1 Indirect instruction addressing [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-,
[ Description Example ]
1
• This instruction logically ORs
• When (.W) is specified for the size specifier (.size) and dest is the address register (A0, A1), the 8
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB]
dsp:24[A0] dsp:24[A1] abs24
#IMM8/#IMM16
OR.B
OR.B:G
OR.B:G
OR.B:S
OR.W:G
0 .
OR.size (:format) src,dest
S :
Z :
0
high-order bits become 0. Also, when src is the address register, the 16 low-order bits of the address
register are the data to be operated on.
0
5
R1L/R1/R3R1, R1H/R3/-, SP/SP/SP, and #IMM.
3 .
U
1
The flag is set when the transfer resulted in MSB of dest = 1; otherwise cleared.
The flag is set when the transfer resulted in 0; otherwise cleared.
p
src
[src]
a
I
g
e
dsp:8[A1]
A1/A1/A1
Ram:8[SB],R0L
A0,R0L
R0L,A0
#3,R0L
[R1],[[A0]]
38
O
dest
dest
B
f o
3
3
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
5
src
Z
dest
D
and
[A1]
dsp:8[FB]
abs16
C
src
[dest]
[dest]
Logically OR
115
together and stores the result in
G , S (Can be specified)
B , W
OR
(See the next page for src/dest classified by format.)
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB]
dsp:24[A0] dsp:24[A1] abs24
src
[src]
; A0's 8 low-order bits and R0L are ORed.
; R0L is zero-expanded and ORed with A0.
[ Instruction Code/Number of Cycles ]
A1/A1/A1
dsp:8[A1]
[dest]
[dest]
3.1 Guide to This Chapter
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dest
.
dest
3.2 Functions
[A1]
dsp:8[FB]
abs16
Page=260
OR