M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 344

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Chapter 6
Figure 6.1.4. When executing an instruction to read from odd addresses starting from an even address
1 .
0
9
0 .
B
0
0
Instructions
under execution
Fetch code
Data bus (H)
Instruction
queue buffer
BCLK
Address bus
Data bus (L)
WR
RD
3
1
Content at jump
address is prefetched at
the same time the
instruction queue buffer
is cleared.
2
9
0
0 -
0
6
1
0 .
0
0
5
3 .
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Calculation number of cycles
DR : Indicates a data read.
1
Sample program
Address
FFC024
FFC024
FFC025
FFC026
FFC027
FFC028
FFC029
FFC02A
FFC02B
FFC02C
FFC02C
FFC030
FFC031
FFC032
FFC033
FFC034
FFC035
FFC036
FFC037
FFC038
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
Jump address
p
: Indicates the locations of the instruction queue buffer that are cleared.
FFC02A FFC02C FFC02E FFC030
a
g
7A
DE
DE
DE
DE
DE
DE
DE
e
JMP TEST_11
DE
DE
P
326
Code
7A
DE
DE
DE
DE
DE
DE
DE
B9FB0120
7A
DE
DE
DE
DE
DE
DE
DE
B9
FB
TEST_11:
TEST_12:
TEST_10:
f o
FB
B9
P
3
3
5
B9
FB
01
20
P
20
01
Instruction
Fetch
B9FB
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W:G
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DE
01
20
7A
DE
7A
P
Fetch
0020
02001
DE
7A
DR
MOV.W
AA
TEST_11
02001h,R1
TEST_12
02002
DE
7A
Content at address 2001
DR
AA
FFC032 FFC034 FFC038 FFC03A
DE
DE
DE
Content at address 2002
7A
P
DE
DE
Fetch
DE
DE
DE
DE
DE
7A
JMP TEST_12
DE
DE
P
16
FB
B9
6.1 Instruction queue buffer
FB
B9
P
Content at jump address
is prefetched at the
same time the instruction
queue buffer is cleared.
16
B9
FB
01
20
P
20
01