M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 332

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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5.3 Interrupt Sequence
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Chapter 5
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU,
SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed,
and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
After the interrupt sequence is completed, the processor resumes executing instructions from the first ad-
dress of the interrupt routine.
Note: This register cannot be utilized by the user.
1 .
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. Saves in the flag
(5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register (SVP)
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
0
5.2.4 Rewrite the interrupt control register
9
0 .
B
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
000000
in the temporary register (Note) within the CPU.
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through
63, is executed)
save register (SVF) in high-speed interrupt.
in high-speed interrupt.
0
0
3
1
2
9
0
0 -
0
6
1
0 .
16
0
0
5
(address 000002
3 .
Interrupt
1
p
a
g
e
314
f o
16
3
3
when high-speed interrupt).
5
5.2 Interrupt Control