M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 118

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
LDCTX
[ Syntax ]
[ Function ]
[ Flag Change ]
[ Description Example ]
v
J
Change
1 .
0
Chapter 3
9
LDCTX
Flag
0 .
B
• This instruction restores task context from the stack area.
• Set the RAM address that contains the task number in abs16 and the start address of table data in abs24.
• The required register information is specified from table data by the task number and the data in the stack area is
• Information on transferred registers is configured as shown below. Logic 1 indicates a register to be
LDCTX
• The table data is comprised as shown below. The address indicated by abs24 is the base address of
0
0
transferred to each register according to the specified register information. Then the SP correction value is
added to the stack pointer (SP). For this SP correction value, set the number of bytes you want to the trans-
ferred. Calculated as 2 bytes when transferring the R0, R1, R2, or R3 registers. A0, A1, SB, and FB
are calculated as 4 bytes.
transferred and logic 0 indicates a register that is not transferred.
the table. The data stored at an address apart from the base address as much as twice the content of
abs16 indicates register information, and the next address contains the stack pointer correction value.
3
1
2
9
0
abs24
0 -
U
0
6
1
0 .
0
0
5
I
3 .
1
abs16,abs24
Ram,Rom_TBL
Functions
Direction in
which address
increases
O
p
Base address
of table
a
g
e
B
100
S
f o
Z
3
3
Register information for the task whose task number = n
SP correction value for the task whose task number = n
5
Register information for the task whose task number = 0.
Register information for the task whose task number = 1.
SP correction value for the task whose task number = 0.
SP correction value for the task whose task number = 1.
MSB
D
FB SB A1 A0 R3 R2 R1 R0
C
LoaD ConTeXt
Restore context
(See the above diagram.)
(See the above diagram.)
(See the above diagram.)
[ Instruction Code/Number of Cycles ]
LSB
Transferred sequentially beginning
with R0
*1
.
*1
.
*1
abs16
LDCTX
n=0 to 255
3.2 Functions
2
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