M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 340

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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6.1 Instruction queue buffer
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Chapter 6
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The M32C/80 Series have 8-stage (8-byte) instruction queue buffers. If the instruction queue buffer has a
free space when the CPU can use the bus, instruction codes are taken into the instruction queue buffer.
This is referred to as “prefetch”. The CPU reads (fetches) these instruction codes from the instruction
queue buffer as it executes a program.
Explanation about the number of cycles in Chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that data is read or written to the memory connected via a 16-bit
bus (including the internal memory) beginning with even addresses without software wait or RDY or other
wait states. In the following cases, more cycles may be needed than the number of cycles shown in this
manual:
Note that if prefetch and data access occur in the same timing, data access has priority. Also, if more than
seven bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space in the instruction queue buffer and, therefore, does not prefetch instruction code.
Figures 6.1.1 to 6.1.8 show examples of instruction queue buffer operation and CPU execution cycles.
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• When not all of the instruction codes needed by the CPU are placed in the instruction queue buffer...
• When reading or writing data to an area in which software wait or RDY or other wait states exist...
• When reading or writing 16-bit data to memory chips connected to an 8-bit bus...
• When reading or writing 16-bit data to memory chips connected to a 16-bit bus beginning with an odd
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Instruction codes are read in until all of the instruction codes required for program execution are avail-
able. Furthermore, the number of read cycles increases in the following cases:
The number of read or write cycles increases as many as the number of wait cycles incurred.
The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write
cycles increases by one for each 16-bit data read or written.
address...
The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write
cycles increases by one for each 16-bit data read or written.
(1) The number of read cycles increases as many as the number of wait cycles incurred when reading
(2) When reading instruction codes from memory chips connected to an 8-bit bus, more read cycles are
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2
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instruction codes from an area in which software wait or RDY or other wait states exist.
required than for 16-bit bus.
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Calculation number of cycles
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322
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3
5
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6.1 Instruction queue buffer
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