M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 133

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
[ Function ]
v
OR
[ Syntax ]
[ Operation ]
[ Selectable src/dest ]*
[ Description Example ]
[ Flag Change ]
J
Chapter 3 Functions
*1 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0,
*2 If you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
Change
1 .
0
Conditions
#IMM8/#IMM16
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB]
dsp:24[A0] dsp:24[A1] abs24
9
OR.size (:format) src,dest
dest
dest
Flag
0 .
B
• This instruction logically ORs
• When (.B) is specified for the size specifier (.size) and
• When (.W) is specified for the size specifier (.size) and
S :
Z :
OR.B
OR.B:G
OR.B:G
OR.B:S
OR.W:G
0
R0H/R2/-, R1L/R1/R3R1,
taneously.
0
extended to be treated as 16-bit data for the operation. In this case, the 8 high-order bits become 0.
Also, when
be operated on.
bits become 0. Also, when
the data to be operated on.
3
1
2
9
0
0 -
0
U
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
6
1
0 .
2
0
0
src
[src]
5
A1/A1/A1*
I
3 .
1
Ram:8[SB],R0L
A0,R0L
R0L,A0
#3,R0L
[R1],[[A0]]
src
O
p
a
is the address register, the 8 low-order bits of the address register are used as data to
g
e
dest
B
dest
2
1
115
src
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
S
f o
R1H/R3/-,
Z
3
[A1]
src
3
5
dest
D
is the address register, the 16 low-order bits of the address register are
dsp:8[FB]
abs16
and
C
and #IMM.
[dest]
[dest]
G , S (Can be specified)
B , W
src
Logically OR
together and stores the result in
(See the next page for
OR
src
[src]
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0] dsp:8[A1]
dsp:16[A0] dsp:16[A1] dsp:16[SB] dsp:16[FB]
dsp:24[A0] dsp:24[A1] abs24
; A0's 8 low-order bits and R0L are ORed.
; R0L is zero-expanded and ORed with A0.
dest
dest
is the address register (A0, A1),
2
[dest]
[dest]
[ Instruction Code/Number of Cycles ]
A1/A1/A1*
is the address register, the 8 high-order
src
2
dest
/
dest
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dest
classified by format.)
.
[A1]
src
3.2
and
dsp:8[FB]
abs16
src
dest
Page=
Functions
OR
is zero-
simul-
264