M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 122

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
MOV
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]*
[ Flag Change ]
[ Description Example ]
J
Chapter 3 Functions
*1 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-,
*2 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
*3 When
1 .
Change
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM
Conditions
9
MOV.size (:format) src,dest
dest
dest
Flag
0 .
B
• This instruction transfers
• When (.B) is specified for the size specifier (.size) and
• When (.W) is specified for the size specifier (.size) and
• When (.L) is specified for the size specifier (.size) and
S :
Z :
0
R1L/R1/R3R1, R1H/R3/-, dsp:8[SP], and #IMM.
simultaneously.
0
MOV.B:S
MOV.W
MOV.W
extended to be treated as 16-bit data for the operation. In this case, the 8 high-order bits become 0.
Also, when
be operated on.
bits become 0. Also, when
the data to be operated on.
of
register,
states depending on the result of 32-bit operation.
3
1
2
9
0
src
0 -
U
0
The flag is set when the transfer resulted in MSB = 1; otherwise cleared.
The flag is set when the transfer resulted in 0; otherwise cleared.
6
src
1
2
0 .
0
is ignored and the 24 low-order bits of
src
[src]
0
5
I
3 .
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
dsp:8[SP]*
or
src
1
src
dest
#0ABH,R0L
#-1,R2
[A1],[[A0]]
O
is zero-extended to be treated as 32-bit data for the operation. The flags also change
p
a
is the address register, the 8 low-order bits of the address register are used as data to
g
is dsp:8[SP], you cannot choose indirect instruction addressing [src] nor [dest].
e
B
1
src
104
2
3
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
[dest]
[dest]
f o
src
Z
3
src
3
5
to
D
is the address register, the 16 low-order bits of the address register are
dest
[src]
C
src
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
.
G , Q , Z , S
B , W , L
Transfer
MOVe
(See the next page for src/dest classified by format.)
src
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
dsp:8[SP]*
is stored to
(Can be specified)
dest
dest
dest
is the address register, the 8 high-order bits
is the address register (A0, A1),
2
3
[ Instruction Code/Number of Cycles ]
is the address register, the 8 high-order
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
dest
. Also, when
dest
2
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
src
3.2 Functions
is the address
src
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
MOV
src
Page=
and
is zero-
dest
245