M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 129

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
MULU
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ] *
[ Flag Change ]
[ Description Example ]
J
Chapter 3 Functions
*1 When the size specifier (.size) is (.B), indirect instruction addressing [src] and [dest] can be used in all addressing
*2 When you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
1 .
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16/#IMM32
Change
9
MULU.size
dest
dest
0 .
Flag
B
• This instruction multiplies
• When you selected (.B) for the size specifier (.size),
• When you selected (.W) for the size specifier (.size),
• When you selected (.L) for the size specifier (.size),
0
except R0L, R0H, R1L, R1H, and #IMM.
When the size specifier (.size) is (.W), indirect instruction addressing [src] can be used in all addressing
except R0, R1, and #IMM. Indirect instruction addressing [dest] cannot be used in any addressing.
When the size specifier (.size) is (.L), no indirect instruction addressing can be used.
simultaneously.
0
operation and the result is stored in 16 bits. When you specified an address register (A0, A1) for either
src
register, the 8 high-order bits become 0.
operation and the result is stored in 32 bits. R0, R1, A0, and A1 can be selected for
specified R0 or R1 for
register is selected for
address register is selected for
operation and the result is stored in 32 bits. R2R0 is selected for
selected for
order bits are valid for the result.
3
1
2
MULU.B
MULU.W
MUL.L
9
0
0 -
or
0
U
6
1
0 .
dest
2
0
dest
dest
0
5
3 .
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
I
, operation is performed on the address register's 8 low-order bits. When
1
src,dest
src
O
p
A0,R0L
#3,R0
A0,R2F0
a
,
g
e
src
src
[src]
B
1
111
src
2
is zero-extended to be treated as 32-bit data for the operation, and only 32-low-
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
dest
dest
f o
src
3
Z
3
, the 24 low-order bits of the 32-bit operation result is stored. When the
, the result is stored in R2R0 or R3R1 accordingly. When the address
5
and
[dest]
[dest]
D
src
dest
, operation is performed using the 16 low-order bits of the register.
MULtiple Unsigned
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
Unsigned multiply
together not including the sign bits and stores the result in
B , W , L
[dest]
[dest]
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
src
src
src
; R0L and A0's 8 low-order bits are multiplied.
[src]
src
and
and
and
2
dest
dest
dest
[ Instruction Code/Number of Cycles ]
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
both are treated as 32-bit data for the
both are treated as 16-bit data for the
both are treated as 8-bit data for the
dest
. When the address register is
dest
2
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
dest
dest
3.2 Functions
MULU
is the address
src
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
. When you
Page=
and
dest
dest
260
.