MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 86

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.6.9 Reset Status Register
4.7 Interrupts
4.7.1 Interrupt Exception Processing
4.7.2 Interrupt Priority and Recognition
4-46
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when the RESET signal is released. Refer
to APPENDIX D REGISTER SUMMARY.
Interrupt recognition and servicing involve complex interaction between the system in-
tegration module, the central processing unit, and a device or module requesting in-
terrupt service. This discussion provides an overview of the entire interrupt process.
Chip-select logic can also be used to respond to interrupt requests. Refer to 4.8 Chip
Selects for more information.
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing. Each exception has an assigned vector in
an exception vector table that points to an associated handler routine. The CPU uses
vector numbers to calculate displacement into the table. During exception processing,
the CPU fetches the appropriate vector and executes the exception handler routine to
which the vector points.
Out of reset, the exception vector table is located beginning at address $000000. This
value can be changed by programming the vector base register (VBR) with a new val-
ue, and multiple vector tables can be used. Refer to SECTION 5 CENTRAL PRO-
CESSING UNIT for more information concerning exceptions.
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less
than seven can be masked by the interrupt priority (IP) field in status register.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally
on the IMB, and are corresponding pins for external interrupt service requests. The
CPU treats all interrupt requests as though they come from internal modules — exter-
nal interrupt requests are treated as interrupt service requests from the SIM. Each of
the interrupt request signals corresponds to an interrupt priority level. IRQ1 has the
lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask
value. The interrupt priority mask consists of three bits in the CPU32 status register.
Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt
request of a priority less than or equal to the mask value from being recognized and
processed. IRQ7, however, is always recognized, even if the mask value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted
until an interrupt acknowledge cycle corresponding to that level is detected.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
USER’S MANUAL
MC68332