MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 125

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

6.2.1.2 Freeze Operation
6.2.1.3 QSM Interrupts
6.2.2 QSM Pin Control Registers
MC68332
USER’S MANUAL
The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken
by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ0 has no effect;
setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE
assertion. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information
about background debugging mode.
Both the QSPI and SCI can make interrupt requests on the IMB. Each has a separate
interrupt request priority register, but a single vector register is used to generate ex-
ception vector numbers.
The values of the ILQSPI and ILSCI fields in the QILR determine the priority of QSPI
and SCI interrupt requests. The values in these fields correspond to internal interrupt
request signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM
interrupt request is made; lower field values cause corresponding lower-numbered in-
terrupt request signals to be asserted. Setting field value to %000 disables interrupts.
If ILQSPI and ILSCI have the same nonzero value, and the QSPI and SCI make simul-
taneous interrupt requests, the QSPI has priority.
When the CPU32 acknowledges an interrupt request, it places the value in the inter-
rupt priority (IP) mask in the CPU status register on the address bus. The QSM com-
pares IP mask value to request priority to determine whether it should contend for
arbitration priority. Arbitration priority is determined by the value of the IARB field in the
QSMCR. Each module that generates interrupts must have a nonzero IARB value. Ar-
bitration is performed by means of serial assertion of IARB field bit values.
When the QSM wins interrupt arbitration, it responds to the CPU interrupt acknowl-
edge cycle by placing an interrupt vector number on the data bus. The vector number
is used to calculate displacement into the CPU32 exception vector table. SCI and
QSPI vector numbers are generated from the value in the QIVR INTV field. The values
of bits INTV[7:1] are the same for QSPI and SCI, but the value of INTV0 is supplied by
the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt requests;
INTV0 = 1 for QSPI requests.
At reset, INTV is initialized to $0F, the uninitialized interrupt vector number. To enable
interrupt-driven serial communication, a user-defined vector number ($40–$FF) must
be written to QIVR, and interrupt handler routines must be located at the addresses
pointed to by the corresponding vector. CPU writes to INTV0 have no meaning or ef-
fect. Reads of INTV0 return a value of one.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
The QSM uses nine pins. Eight of the pins can be used for serial communication or for
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns
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