MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 79

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.6.3.1 Data Bus Mode Selection
MC68332
USER’S MANUAL
All data lines have weak internal pull-up drivers. When pins are held high by the inter-
nal drivers, the MCU uses a default operating configuration. However, specific lines
can be held low externally to achieve an alternate configuration.
Use an active device to hold data bus lines low. Data bus configuration logic must re-
lease the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is re-
leased. If external mode selection logic causes a conflict of this type, an isolation re-
sistor on the driven lines may be required. Figure 4-15 shows a recommended method
for conditioning the mode select signals.
Mode Select Pin
MODCLK
DATA11
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
BKPT
External bus loading can overcome the weak internal pull-up drivers
on data bus lines, and hold pins low during reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-16 Reset Mode Selection
SYSTEM INTEGRATION MODULE
Background Mode Disabled
VCO = System Clock
Test Mode Disabled
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Default Function
CSBOOT 16-Bit
(Pin Left High)
AVEC, DS, AS,
DSACK[1:0],
MODCLK
CS[10:6]
IRQ[7:1]
CS[7:6]
CS[8:6]
CS[9:6]
SIZE
CS0
CS1
CS2
CS3
CS4
CS5
CS6
NOTE
Background Mode Enabled
EXTAL = System Clock
Alternate Function
Test Mode Enabled
(Pin Pulled Low)
CSBOOT 8-Bit
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
ADDR19
BGACK
PORTE
PORTF
FC0
FC1
FC2
BG
BR
4-39