MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 106

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.4 Virtual Memory
5.5 Addressing Modes
5.6 Processing States
5-8
The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight
address spaces. Even though most systems implement a smaller physical memory,
the system can be made to appear to have a full 16 Mbytes of memory available to
each user program by using virtual memory techniques.
A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger virtual memory on a secondary storage device. When the processor at-
tempts to access a location in the virtual memory map that is not resident in physical
memory, a page fault occurs. The access to that location is temporarily suspended
while the necessary data is fetched from secondary storage and placed in physical
memory. The suspended access is then restarted or continued.
The CPU32 uses instruction restart, which requires that only a small portion of the in-
ternal machine state be saved. After correcting the fault, the machine state is restored,
and the instruction is fetched and started again. This process is completely transpar-
ent to the application program.
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory. There is no
need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
The register indirect addressing modes include postincrement, predecrement, and off-
set capability. The program counter indirect mode also has index and offset capabili-
ties. In addition to these addressing modes, many instructions implicitly specify the
use of the status register, stack pointer, and/or program counter.
The processor is always in one of four processing states: normal, exception, halted, or
background. The normal processing state is associated with instruction execution; the
bus is used to fetch instructions and operands and to store results.
The exception processing state is associated with interrupts, trap instructions, tracing,
and other exception conditions. The exception may be internally generated explicitly
by an instruction or by an unusual condition arising during the execution of an instruc-
tion. Exception processing can be forced externally by an interrupt, a bus error, or a
• Register Direct
• Register Indirect
• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
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USER’S MANUAL
MC68332