MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 84

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.6.7 Power-On Reset
4-44
If an internal source asserts a reset signal, the reset control logic asserts RESET for
a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles,
the control logic continues to assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the reset input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the reset
input is at logic level zero, the reset control logic drives the pin low for another 512 cy-
cles. At the end of this period, the pin again goes to high-impedance state for ten cy-
cles, then it is tested again. The process repeats until RESET is released.
When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to clock synthesizer pow-
er input pin V
V
When V
rameters and by oscillator circuit design. V
ing reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and
timing specifications.
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The circuit releases MSTRST as V
the minimum specified value, and SIM pins are initialized as shown in Table 4-19. As
V
and clock frequency ramps up to specified limp mode frequency. The external RESET
line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles
elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 4-16 is a timing diagram of power-up reset. It shows the relationships between
RESET, V
DDSYN
DD
reaches specified minimum value, the clock synthesizer VCO begins operation
DD
DDSYN
is applied before and during reset, which minimizes crystal start-up time.
DD
ramp time and VCO frequency ramp time determine how long the four cy-
, and bus signals.
DDSYN
is applied at power-on, start-up time is affected by specific crystal pa-
Freescale Semiconductor, Inc.
for the MCU to operate. The following discussion assumes that
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
DD
ramp-up time also affects pin state dur-
USER’S MANUAL
DD
ramps up to
MC68332