MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 239

IC MCU 32BIT 16MHZ 132-PQFP

MC68332GCEH16

Manufacturer Part Number
MC68332GCEH16
Description
IC MCU 32BIT 16MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68332GCEH16

Core Processor
CPU32
Core Size
32-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Interface Type
QSPI/SCI/UART
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Controller Family/series
68K
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
2 KB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
15
Number Of Timers
16
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68332GCEH16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
D.4.10 SPCR0 — QSPI Control Register 0
MSTR — Master/Slave Mode Select
MC68332
USER’S MANUAL
RESET:
MSTR
15
0
DDRQS determines the direction of the TXD pin only when the SCI transmitter is dis-
abled. When the SCI transmitter is enabled, the TXD pin is an output.
SPCR0 contains parameters for configuring the QSPI and enabling various modes of
operation. The CPU has read/write access to SPCR0, but the QSM has read access
only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to
SPCR0 while the QSPI is enabled disrupts operation.
0 = QSPI is a slave device.
1 = QSPI is system master.
NOTES:
WOMQ
14
0
QSM Pin
PCS0/SS
PCS[3:1]
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case
MISO
MOSI
SCK
TXD
RXD
SPI serial clock SCK.
it becomes SCI serial output TXD.
1
2
13
0
0
BITS
Transmit
Freescale Semiconductor, Inc.
Receive
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
For More Information On This Product,
0
Effect of DDRQS on QSM Pin Function
10
0
Go to: www.freescale.com
REGISTER SUMMARY
CPOL
DDRQS Bit
9
0
DDQS0
DDQS1
DDQS2
DDQS3
DDQS7
DDQS
None
[4:6]
CPHA
8
1
7
0
State
NA
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
0
0
Serial Data Input to QSPI
Disables Data Input
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
QSPI Slave Select Input
Disables Select Input
Chip-Select Output
Inactive
Inactive
Serial Data Output from SCI
Serial Data Input to SCI
Disables Chip-Select Output
0
Pin Function
0
SP
0
1
$YFFC18
0
D-25
0
0

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