MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 33

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

3.5 Intermodule Bus
3.6 System Memory Map
MC68332
USER’S MANUAL
Function Codes
Freeze
Halt
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
Clock Mode Select
Master Out Slave In
Port C
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
Port F
Port QS
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
TCR2 Clock
TPU Channel Pins
Three-State Control
SCI Transmit Data
External Filter Capacitor
The intermodule bus (IMB) is a standardized bus developed to facilitate both design
and operation of modular microcontrollers. It contains circuitry to support exception
processing, address space partitioning, multiple interrupt levels, and vectored inter-
rupts. The standardized modules in the MCU communicate with one another and with
external components through the IMB. The IMB in the MCU uses 24 address and 16
data lines.
Figure 3-4 through Figure 3-8 are MCU memory maps. Figure 3-4 shows IMB ad-
dresses of internal registers. Figure 3-5 through Figure 3-8 show system memory
maps that use different external decoding schemes.
Signal Name
Table 3-5 MCU Signal Function (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
IPIPE, IFETCH Indicate instruction pipeline activity
TPUCH[15:0]
Mnemonic
MODCLK
PCS[3:0]
PQS[7:0]
FREEZE
IRQ[7:1]
SIZ[1:0]
PC[6:0]
RESET
FC[2:0]
PE[7:0]
PF[7:0]
T2CLK
QUOT
PCLK
HALT
MISO
MOSI
RMC
RXD
SCK
R/W
TSC
TXD
XFC
SS
Go to: www.freescale.com
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Selects the source and type of system clock
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
SIM digital output port signals
External clock dedicated to the GPT
QSPI peripheral chip selects
SIM digital I/O port signals
SIM digital I/O port signals
QSM digital I/O port signals
Provides the quotient bit of the polynomial divider
System reset
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
Serial input to the SCI
Clock output from QSPI in master mode;
clock input to QSPI in slave mode
Indicates the number of bytes to be transferred during a bus cycle
Causes serial transmission when QSPI is in slave mode;
causes mode fault in master mode
External clock source for TCR2 counter
Bidirectional pins associated with TPU channels
Places all output drivers in a high-impedance state
Serial output from the SCI
Connection for external phase-locked loop filter capacitor
OVERVIEW
Function
3-9