MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 168

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

7.6.2 Channel Control Registers
7.6.2.1 Channel Interrupt Enable and Status Registers
7.6.2.2 Channel Function Select Registers
7.6.2.3 Host Sequence Registers
7.6.2.4 Host Service Registers
7.6.2.5 Channel Priority Registers
7-14
The channel control and status registers enable the TPU to control channel interrupts,
assign time functions to be executed on a specified channel, or select the mode of op-
eration or the type of host service request for the time function specified. Refer to Ta-
ble 7-3.
The channel interrupt enable register (CIER) allows the CPU to enable or disable the
ability of individual TPU channels to request interrupt service. Setting the appropriate
bit in the register enables a channel to make an interrupt service request; clearing a
bit disables the interrupt.
The channel interrupt status register (CISR) contains one interrupt status flag per
channel. Time functions specify via microcode when an interrupt flag is set. Setting a
flag causes the TPU to make an interrupt service request if the corresponding CIER
bit is set and the CIRL field has a nonzero value. To clear a status flag, read CISR,
then write a zero to the appropriate bit. CISR is the only TPU register that can be ac-
cessed on a byte basis.
Encoded 4-bit fields within the channel function select registers specify one of 16 time
functions to be executed on the corresponding channel. Encodings for predefined
functions in the TPU ROM are found in Table 7-3.
The host sequence field selects the mode of operation for the time function selected
on a given channel. The meaning of the host sequence bits depends on the time func-
tion specified. Refer to Table 7-3, which is a summary of the host sequence and host
service request bits for each time function.
The host service request field selects the type of host service request for the time func-
tion selected on a given channel. The meaning of the host service request bits is de-
termined by time function microcode.
A host service request field cleared to %00 signals the host that service is completed
by the microengine on that channel. The host can request service on a channel by writ-
ing the corresponding host service request field to one of three nonzero states. It is a
good practice to monitor the host service request register and wait until the TPU clears
the service request before changing any parameters or issuing a new service request
to the channel.
The channel priority registers (CPR1, CPR2) assign one of three priority levels to a
channel or disable the channel. Table 7-3 indicates the number of time slots guaran-
teed for each channel priority encoding.
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TIME PROCESSOR UNIT
USER’S MANUAL
MC68332