MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 119

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

MC68332
USER’S MANUAL
MICROSEQUENCER
The serial interface uses a full-duplex synchronous protocol similar to the serial pe-
ripheral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the oper-
ating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode — data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide — 16 data bits and a status/control bit. Bit 16 in-
dicates the status of CPU-generated messages as shown in Table 5-6.
SYNCHRONIZE
EXECUTION
CPU
STATUS
UNIT
Figure 5-9 Debug Serial I/O Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
RCV DATA LATCH
REGISTER BUS
PARALLEL OUT
INSTRUCTION
CENTRAL PROCESSING UNIT
SERIAL IN
PARALLEL IN
SERIAL OUT
Go to: www.freescale.com
16
16
CONTROL
LOGIC
M
DSCLK
DSO
DSI
STATUS
0
DEVELOPMENT SYSTEM
COMMAND LATCH
CONTROL
PARALLEL OUT
RESULT LATCH
PARALLEL IN
SERIAL OUT
LOGIC
SERIAL IN
DATA
DATA
16
16
SERIAL
CLOCK
32 DEBUG I/O BLOCK
5-21