MC68332GCEH16 Freescale Semiconductor, MC68332GCEH16 Datasheet - Page 117

• Manufacturer Part Number: MC68332GCEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.10.2.4 BDM Commands
MC68332
USER’S MANUAL
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence
is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other
time will the processor write an odd value into this register.
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the com-
mand is complete. Result operands are loaded into the output shift register to be shift-
ed out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. Table 5-5 is a summary of background
mode commands.
Read Memory Location
Write Memory Location
Read System Register
Write System Register
Dump Memory Block
Read D/A Register
Resume Execution
Write D/A Register
Fill Memory Block
Reset Peripherals
Patch User Code
No Operation
Command
Table 5-5 Background Mode Command Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSING UNIT
WDREG/WAREG The data operand is written to the specified
RDREG/RAREG
Go to: www.freescale.com
Mnemonic
WSREG
RSREG
WRITE
DUMP
READ
CALL
NOP
FILL
RST
GO
Read the selected address or data register and
The specified system control register is read. All
The operand data is written into the specified
Read the sized data at the memory location
Write the operand data to the memory location
Used in conjunction with the READ command to
Used in conjunction with the WRITE command to
The pipe is flushed and re-filled before resuming
Current program counter is stacked at the
Asserts RESET for 512 clock cycles. The CPU is
NOP performs no operation and may be used as
return the results via the serial interface.
address or data register.
registers that can be read in supervisor mode
can be read in background mode.
system control register.
specified by the long-word address. The
source function code register (SFC)
determines the address space accessed.
specified by the long-word address. The
destination function code (DFC) register
determines the address space accessed.
dump large blocks of memory. An initial READ
is executed to set up the starting address of
the block and retrieve the first result.
Subsequent operands are retrieved with the
DUMP command.
fill large blocks of memory. An initial WRITE is
executed to set up the starting address of the
block and supply the first operand.
Subsequent operands are written with the
FILL command.
instruction execution at the current PC.
location of the current stack pointer.
Instruction execution begins at user patch
code.
not reset by this command. Synonymous with
the CPU RESET instruction.
a null command.
Description
5-19