Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 98

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Architecture
Operation
PS022008-0810
Master Interrupt Enable
Figure 18
The master interrupt enable bit in the flag register globally enables or disables interrupts.
This bit has been moved to the flag register (bit-0). Thus, anytime the register is loaded, it
changes the state of the IRQE bit. For the
been pushed on the stack.
Interrupts are globally enabled by any of the following actions:
•
•
Interrupts are globally disabled by any of the following actions:
•
•
•
Internal Interrupts
Port Interrupts
controller
Execution of an Enable Interrupt (
Writing 1 to the IRQE bit in the flag register
Execution of a Disable Interrupt (
ZNEO CPU acknowledgement of an interrupt service request from the interrupt
Writing 0 to the IRQE bit in the flag register
displays a block diagram of the interrupt controller.
Figure 18. Interrupt Controller Block Diagram
P R E L I M I N A R Y
DI
EI
Medium
Priority
Priority
Priority
High
Low
) instruction
) instruction
IRET
instruction the bit is set based on what has
Priority
Mux
Vector
Product Specification
IRQ Request
ZNEO
Interrupt Controller
Z16F Series
83