Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 208

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 98. ESPI Data Register (ESPIDATA)
Table 99. ESPI Transmit Data Command Register (ESPITDCR)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
ESPI Transmit Data Command Register
R/W
R
7
X
7
0
load the Transmit Data register unless
last bit received resides in bit position 0.
With the ESPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the ESPI configured as a Slave, writing a data byte to this register
loads the shift register in preparation for the next data transfer with the external Master. In
either the Master or Slave modes, if TDRE = 0, writes to this register are ignored.
When the character length is less than 8 bits (as set by the NUMBITS field in the ESPI
Mode register), the transmit character must be left justified in the ESPI Data register. A
received character of less than 8 bits is right justified (last bit received is in bit position 0).
For example, if the ESPI is configured for 4-bit characters, the transmit characters must be
written to ESPIDATA[7:4] and the received characters are read from ESPIDATA[3:0].
DATA—Data
Transmit and/or receive data. Writes to the ESPIDATA register load the shift register.
Reads from the ESPIDATA register return the value of the receive data register.
The ESPI Transmit Data Command register (see
when it is configured as an output (MASTER mode). The TEOF and SSV bits are
controlled by the DMA interface as well as by a bus write to this register.
R/W
X
R
6
6
0
R/W
R
5
X
5
0
P R E L I M I N A R Y
R/W
X
R
4
4
0
FF_E260H
FF_E261H
TDRE = 0
DATA
R/W
. Data is shifted out starting with bit 7. The
R
3
X
3
0
Table
Enhanced Serial Peripheral Interface
99) provides control of the SS pin
R/W
X
R
2
2
0
Product Specification
ZNEO
TEOF
R/W
R/W
1
X
1
0
Z16F Series
R/W
SSV
R/W
X
0
0
0
192