Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 209

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 100. ESPI Control Register (ESPICTL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
ESPI Control Register
DIRQE
R/W
7
0
TEOF—Transmit End of Frame
This bit is used in Master mode to indicate that the data in the transmit data register is the
last byte of the transfer or frame. When the last byte has been sent SS (and SSV) change
state and TEOF automatically clears.
0 = The data in the transmit data register is not the last character in the message.
1 = The data in the transmit data register is the last character in the message.
SSV—Slave Select Value
When SSIO = 1, writes to this register controls the value output on the SS pin. See SSMD
field of the ESPI Mode register for more details.
The ESPI Control register (see
operations.
DIRQE—Data Interrupt Request Enable
This bit is used to disable or enable data (TDRE and RDRF) interrupts. Disabling the data
interrupts is needed when controlling data transfer by DMA or polling. Error interrupts are
not disabled. To block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the
Interrupt Controller.
0 = TDRE and RDRF assertions do not cause an interrupt. 
1 = TDRE and RDRF assertions will cause an interrupt.
ESPIEN1, ESPIEN0—ESPI Enable and Direction Control
00 = ESPI block is disabled. 
01 = RECEIVE ONLY Mode.
Use this setting if controlling data transfer through DMA or by software polling of
TDRE and RDRF. The
TUND, COL, ABT, and ROVR will also cause interrupts. Use this setting if 
controlling data transfer through interrupt handlers.
BRG is used as a general purpose timer by setting BRGCTL = 1.
Use this setting if the software application is receiving data but not
sending. TDRE will assert, however the transmit interrupt and DMA requests will
not assert. In SLAVE mode, the transmitted data will be all 1s. 
ESPIEN1
R/W
6
0
BRGCTL
R/W
5
0
P R E L I M I N A R Y
TUND
Table
PHASE
,
R/W
COL
4
0
FF_E262H
100) configures the ESPI for transmit and receive
,
ABT
CLKPOL
, and
R/W
3
0
ROVR
Enhanced Serial Peripheral Interface
bits cause an interrupt.
WOR
R/W
2
0
Product Specification
ZNEO
MMEN
R/W
1
0
Z16F Series
ESPIEN0
R/W
0
0
193