Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 91

IC ZNEO MCU FLASH 64K 80QFP

Z16F6411FI20SG

Manufacturer Part Number
Z16F6411FI20SG
Description
IC ZNEO MCU FLASH 64K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet

Specifications of Z16F6411FI20SG

Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F6x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4571

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z16F6411FI20SG
Manufacturer:
LT
Quantity:
121
Part Number:
Z16F6411FI20SG
Manufacturer:
Zilog
Quantity:
10 000
Table 32. Port A-K Output Control Registers (PxOC)
Table 30. Port A-K Alternate Function Low Registers (PxAFL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Port A-K Output Control Registers
FF_E106, FF_E116, FF_E126, FF_E136, FF_E146, FF_E156, FF_E166, FF_E176, FF_E186,
AFL[7]
POC7
R/W
R/W
7
0
7
0
Table 31. Alternate Function Enabling
Setting the bits in the Port A-K output control registers (see
specified port pins for open-drain operation. These registers affect the pins directly and as a
result, alternate functions are also affected. Enabling the I
configures the SCL and SDA pins as open-drain; independent of the setting in the output
control registers that have the SCL and SDA alternate functions.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bits and disable the drains 
if set to 1.
FF_E105, FF_E115, FF_E125, FF_E135, FF_E155, FF_E165, FF_E175, FF_E195
AFH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
AFL[6]
POC6
R/W
R/W
6
0
6
0
AFL[x]
0
1
0
1
AFL[5]
POC5
R/W
R/W
5
5
0
0
P R E L I M I N A R Y
Priority
No Alternate Function Enabled
Alternate Function 1 Enabled
Alternate Function 2 Enabled
Alternate Function 3 Enabled
AFL[4]
POC4
R/W
R/W
4
0
4
0
FF_E196
AFL[3]
POC3
R/W
R/W
3
3
0
0
2
AFL[2]
POC2
C controller automatically
R/W
R/W
Table
2
0
2
0
General-Purpose Input/Output
Product Specification
32) to 1 configures the
ZNEO
AFL[1]
POC1
R/W
R/W
1
1
0
0
Z16F Series
AFL[0]
POC0
R/W
R/W
0
0
0
0
76

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