Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 221

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Table 107. I
Name
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
C Data
C Interrupt Status
C Control
C Baud Rate High
C Baud Rate Low
C State
C Mode
C Slave Address
I
Comparison with Master Mode only I
2
C Master/Slave Controller Registers
2
C Master/Slave Controller Registers
Table 107
Porting code written for the Master-only I
to the I
and I2CBRL register definitions are not changed. The difference between Master-only I
Controller and I
•
•
•
•
•
The I2CMODE register is called as I2CDIAG (Diagnostic Control) register in the MAS-
The Status register (I2CSTATE) from the Master-only I
The I2CSTATE register is called as I2CDST (Diagnostic State) register in the 
The I2CSLVAD register is added for programming the Slave address.
The ACKV bit in the I2CSTATE register enables the Master to verify the 
Interrupt Status (I2CISTAT) register and the State (I2CSTATE) register because there
are more interrupt sources. The
DS) bits formerly in the Status register are moved to the State register.
Master only mode version. The I2CDST register provided diagnostic information. The
I2CSTATE register contains status and state information that are useful to software in
operational mode.
TER ONLY mode version. The I2CMODE register provides control for SLAVE modes
of operation as well as the most significant two bits of the 10-bit Slave address.
acknowledge from the Slave before sending the next byte.
2
C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL, I2CBRH,
summarizes the I
Abbreviation
I2CDATA
I2CISTAT
I2CCTL
I2CBRH
I2CBRL
I2CSTATE
I2CMODE
I2CSLVAD
2
C Master/Slave Controller designs is given below:
P R E L I M I N A R Y
2
C Master/Slave Controller software-accessible registers.
Description
Transmit/Receive Data Register
Interrupt Status Register
Control Register - basic control functions
High byte of baud rate generator initialization value
Low byte of baud rate generator initialization value
State Register
Selects Master or Slave modes, 7-bit or 10-bit addressing
Configure address recognition, Defines Slave Address
bits [9:8]
Defines Slave Address bits [7:0]
ACK
,
10B
2
C Controller found on other Z8 Encore!
2
C Controller
,
TAS
(now called AS) and
2
C Controller is split into the
I
2
C Master/Slave Controller
Product Specification
ZNEO
DSS
Z16F Series
(now called
®
parts
2
C
205