Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 290

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
DMA Modes
Loop Mode Closure
If the LOOP bit is set then the current buffer descriptor is not modified. The DMAxLAR
increments or a new LAR value is fetched from the descriptor.
EOF Closure
The
status data from the peripheral. If the channel is in linked list mode then the DMAxCTL
word is written back to the CONTROL word of the descriptor. The DMAxLAR 
increments or is loaded with new LAR data from the descriptor if the
Normal Closure
The
word is written back to the CONTROL word of the descriptor. The DMAxLAR 
increments or is loaded with new LAR data from the descriptor if the
Each DMA channel operates in two modes, direct and linked list. Both modes use the
DMA channel registers. The only difference is in how they are loaded. In direct mode
the DMA channel registers are directly loaded by software and when the transfer is done
the DMA stops. In linked list mode the DMA will load its own registers from a descrip-
tor list which is pointed to by the DMAxLAR register. It then loads the next descriptor in
the list and continue executing.
The descriptor Control/Status field and address bytes have the same format as the control
and address registers in the DMA.
Direct Mode
Direct mode only uses the registers in the DMA for operation. The software writes these
register directly to setup and enable the DMA. Direct mode is entered by directly setting
the DMAxEN bit in the DMAxCTL0 register.
registers and how they point to the buffers allocated in memory.
DMAxEN
DMAxEN
bit is reset to zero. If the channel is in linked list mode then the DMAxCTL
bit is reset to zero. If the
P R E L I M I N A R Y
EOF
bit is set, the CMDSTAT field is set with the
Figure 57
on page 275 displays the DMA
Product Specification
ZNEO
TXFR
TXFR
DMA Controller
bit is set.
bit is set.
Z16F Series
274