Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 176

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 86. MultiProcessor Control Register (UxCTL1 with MSEL = 000b)
PS022008-0810
FIELD
RESET
R/W
ADDR
BITS
LIN-UART Control 1 Registers
MPMD[1]
R/W
7
0
Multiple registers (see
The register selected is determined by the mode select (
additional control over the LIN-UART operation.
Multiprocessor Control Register (LIN-UART Control 1 Register with
MSEL = 000b)
When
IRDA mode, baud rate timer mode as well as other features which applies to multiple
modes.
break is timed by hardware, and the SBRK bit is deasserted by hardware when the Break is
completed. The duration of the Break is determined by the TxBreakLength field of the LIN
control register. One or two Stop bits are automatically provided by the hardware in LIN
mode as defined by the Stop bit. 
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the address compare register and on all successive data bytes until an
MSEL
address).
MPEN
R/W
6
0
=
000b
MPMD[0]
, this register provides control for UART MULTIPROCESSOR mode,
R/W
FF-E203H, FF-E213H with MSEL = 000b
Table 86
5
0
P R E L I M I N A R Y
through
MPBT
R/W
4
0
Table
DEPOL
R/W
88) are accessible by a single bus address.
3
0
MSEL
BRGCTL
R/W
2
0
) field. These registers provide
Product Specification
ZNEO
RDAIRQ
R/W
1
0
Z16F Series
LIN-UART
IREN
R/W
0
0
160