Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 316

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Operation
PS022008-0810
Caution:
On-Chip Debug Enable
Serial Interface
The DBG pin is mainly used for debugging. The OCD is always enabled by default 
following reset. Disable the OCD after startup and use the DBG pin as a UART or a GPIO
pin if the
To use the DBG pin as a UART or GPIO pin, the OCD must be disabled. The OCD is
disabled by clearing the OCDEN bit in the Debug
cannot be disabled, if the OCDLOCK bit in the DBGCTL register is set.
The DBG pin is used for serial communication. This one-pin interface is a bidirectional
half-duplex open-drain interface that transmits and receives data. Transmit and receive
operations cannot occur simultaneously. The serial data is sent and received using the
asynchronous protocol defined in RS-232. The serial pin is connected to the serial port of
the PC using minimal external hardware. Two different methods for connecting the serial
pin to an RS-232 interface are depicted in
The serial pin is open-drain and must be connected to V
resistor to ensure proper operation.
Figure 62. Interfacing the serial pin with an RS-232 Interface (1)
RS232 TX
RS232 RX
For effective operation of the device, all power pins (V
be supplied with power, and all ground pins (V
erly grounded. The DBG pin must be connected to V
nal pull-up resistor to ensure proper operation.
DBGUART
option bit has been cleared.
RS-232
Tranceiver
P R E L I M I N A R Y
Diode
Figure 62
Vdd
10 k
Control Register
and

SS
DD
DBG pin
Figure
and AV
through an external pull-up
DD
DD
63.
Product Specification
through an exter-
SS
and AV
) must be prop-
ZNEO
(DBGCTL). The OCD
On-Chip Debugger
DD
) must
Z16F Series
300