Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 105

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
IRQ0 Enable High and Low Bit Registers
U1RXI—UART 1 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 1 receiver.
1 = An interrupt request from the UART 1 receiver is awaiting service. Writing 1 to this bit
U1TXI—UART 1 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service. Writing 1 to this
PWMFI— PWM Fault Interrupt Request
0 = No interrupt request is pending for the PWM fault.
1 = An interrupt request from the PWM fault is awaiting service. Writing 1 to this bit
PCxI/DMAxI—Port C Pin x or DMA x Interrupt Request
0 = No interrupt request is pending for GPIO port C pin x or DMA x.
1 = An interrupt request from GPIO port C pin x or DMAx is awaiting service. Writing 1
Where x indicates the specific GPIO port C pin or DMA number (0 through 3).
The IRQ0 enable high and low bit registers (see
encoded enabling for interrupts in the interrupt request 0 register. Priority is generated by
setting bits in each register.
Table 47. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
0
0
1
1
Note: x indicates the register bits from 0 through 7.
Resets it to 0.
bit Resets it to 0.
Resets it to 0.
to this bit Resets it to 0.
IRQ0ENL[x]
P R E L I M I N A R Y
0
1
0
1
Table 47
describes the priority control for IRQ0.
Priority
Disabled
Level 1
Level 2
Level 3
Table 48
High
Description
Disabled
Low
Nominal
and
Table
Product Specification
ZNEO
49) form a priority
Interrupt Controller
Z16F Series
90