Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 216

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 105. ESPI Baud Rate High Byte Register (ESPIBRH)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
ESPI Baud Rate High and Low Byte Registers
R/W
7
1
The ESPI Baud Rate High and Low Byte registers (see
to form a 16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI
baud rate is calculated using the following equation:
Minimum baud rate is obtained by setting BRG[15:0] to
of (2 x 65536 = 131072)
When the ESPI function is disabled, the BRG functions as a basic 16-bit timer with
interrupt on time-out.
Follow the procedure below to configure the BRG as a general purpose timer with
interrupt on timeout:
1. Disable the ESPI by setting
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
BRH = ESPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the ESPI Baud Rate Generator’s reload value.
SPI BRG Interrupt Interval (s)
SPI Baud Rate (bps)
registers.
the ESPI Control register to 1.
R/W
6
1
R/W
5
1
=
P R E L I M I N A R Y
System Clock Frequency (Hz)
--------------------------------------------------------------------------- -
ESPIEN[1:0] = 00
R/W
4
1
2 BRG[15:0]
FF_E266H
=

BRH
System Clock Period (s) BRG[15:0]
R/W
3
1
Enhanced Serial Peripheral Interface
in the SPI Control register.
Table 105
0000H
R/W
2
1
for a clock divisor value
Product Specification
and
ZNEO

Table
R/W
1
1
106) combine
Z16F Series
R/W
0
1
200