Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 229

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Note:
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. The I
12. The I
13. The I
14. Software responds by writing the data to be written out to the I
15. The I
16. The I
17. The I
18. If more bytes remain to be sent, return to step 14.
19. Software responds by asserting the STOP bit of the I
20. The I
21. The I
If the Slave responds with a Not Acknowledge during the transfer, the I
asserts the NCKI bit, sets the
halts. Software terminates the transaction by setting either the STOP bit (end transaction)
register.
asserts.
Data register.
signal.
High period of SCL. The I

If the slave does not acknowledge the first address byte, the I
NCKI bit in the I
State register. Software responds to the Not Acknowledge interrupt by setting the
STOP bit and clearing the
from the data register, sends the STOP condition on the bus and clears the
NCKI
register (2nd address byte).
bit is sent, the Transmit interrupt asserts.
data bytes if looping) by the SDA signal.
High period of SCL. The I

If the slave does not acknowledge, see the second paragraph of step 11 above.
Transmit interrupt asserts.
2
2
2
2
2
2
2
2
2
2
bits. The transaction is complete (ignore the following steps).
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. When the first
C Controller shifts out the rest of the second byte of Slave address (or ensuing
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts the data out by the SDA signal. After the first bit is sent, the
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP condition to the I
2
C Status register, sets the
P R E L I M I N A R Y
ACKV
TXI
2
2
C Controller sets the ACK bit in the I
C Controller sets the ACK bit in the I
2
2
bit. The I
C Shift register with the contents of the I
C Shift register with the contents of the I
bit and clears the
2
C Controller flushes the second address byte
ACKV
ACK
bit and clears the
2
2
bit in the I
C bus.
C Control register.
I
2
C Master/Slave Controller
Product Specification
2
C Controller sets the
ZNEO
2
C Control register.
2
2
2
C Status register.
C State register and
C Status register. 
2
ACK
C Controller
Z16F Series
2
bit in the I
2
C Data
C Data
STOP
and
2
2
C
C
213