Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 234

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Figure 47. Data Transfer Format - Slave Receive Transaction with 7-Bit Address
Slave Transaction Diagrams
In the following transaction diagrams, shaded regions indicate data transferred from the
Master to the Slave and unshaded regions indicate data transferred from the Slave to the
Master. The transaction field labels are defined as follows:
•
•
•
•
•
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from Master to Slave in 7-bit address mode is
shown in
operating as a Slave in 7-bit addressing mode, receiving data from the bus Master.
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
2. The bus Master initiates a transfer, sending the address byte. The Slave mode I
S
S — Start
W — Write
A — Acknowledge
A — Not Acknowledge
P — Stop
– Initialize the MODE field in the I
– Optionally set the
– Initialize the
– Set
– Program the Baud Rate High and Low Byte registers for the I
set when
address byte.
follows.
Controller recognizes its own address and detects the R/W bit = 0 (write from Master
to Slave). The I
transaction.The
The
Controller holds the SCL signal Low, waiting for software to load the first data byte.
or Master/Slave mode with 7-bit addressing.
RD
Figure
Address
IEN
Slave
bit in the I2CISTAT register is set = 0, indicating a write to the Slave. The I
IRM
= 1 in the I
47. The following procedure describes the I
= 1 during the address phase, but the
SLA
2
SAM
C Controller acknowledges, indicating it is available to accept the
[6:0] bits in the I
W=0 A
GCE
bit in the I2CISTAT register is set = 1, causing an interrupt. 
2
P R E L I M I N A R Y
C Control register. Set
bit
Data
2
2
C Mode register for either SLAVE-ONLY mode
C Slave Address register.
A
NAK
Data
= 0 in the I
RD
bit is updated based on the first
2
C Master/Slave Controller
I
A
2
C Master/Slave Controller
Product Specification
2
C Control register.
ZNEO
2
Data
C baud rate.
Z16F Series
A/A
2
C
P/S
2
C
218