Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 77

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Stop Mode Recovery
PS022008-0810
External Pin Reset
External Reset Indicator
User Reset
Fault Detect Logic Reset
The input-only RESET pin has a schmitt-triggered input, an internal pull-up, an analog
filter and a digital filter to reject noise. Once the RESET pin is asserted for at least four
system clock cycles, the device progresses through the System Reset sequence. While the
RESET input pin is asserted Low, the ZNEO Z16F Series device continues to be held in
the Reset state. If the RESET pin is held Low beyond the System Reset time-out, the
device exits the Reset state 16 system clock cycles following RESET pin deassertion.
If the RESET pin is released before the System Reset time-out, the RESET pin is driven
Low by the chip until the completion of the time-out as described in the next section. In
STOP mode, the digital filter is bypassed as the system clock is disabled.
Following a System Reset initiated by the external RESET pin, the EXT status bit in the
Reset Status and Control Register
During System Reset, the RESET pin functions as an open drain (active Low) RESET
mode indicator in addition to the input functionality. This Reset output feature allows a
ZNEO Z16F Series device to Reset other components to which it is connected, even if the
Reset is caused by internal sources such as POR, VBO, or WDT events and as an
indication of when the reset sequence completes.
Once an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in
A System Reset is initiated by setting RSTSCR[0]. If the Write was caused by the OCD,
the OCD is not Reset.
Fault detect circuitry exists to detect Illegal state changes which is caused by transient
power or electrostatic discharge events. When such a fault is detected, a system reset is
forced. Following the system reset, the
on page 64 is set.
STOP mode is entered by execution of a
information on STOP mode, see
Recovery, the device is held in Reset for 66 cycles of the internal precision oscillator.
Table 18
on page 58 has elapsed.
P R E L I M I N A R Y
Low-Power Modes
on page 64 is set to 1.
FLTD
STOP
bit in the
instruction by the ZNEO CPU. For detailed
on page 66. During Stop Mode
Reset Status and Control Register
Reset and Stop Mode Recovery
Product Specification
ZNEO
Z16F Series
62