Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 238

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
S
Slave Address
1st Byte
Figure 50. Data Transfer Format - Slave Transmit Transaction with 10-Bit Address
12. Software responds to the STOP/RESTART interrupt by reading the I2CISTAT register
Slave Transmit (Master Read) Transaction with 10-Bit Address
Figure 50
bit addressing.
The following procedure describes the I
10-bit addressing mode, transmitting data to the bus Master:
1. Software configures the controller for operation as a Slave in 10-bit addressing mode.
2. The Master initiates a transfer, sending the first address byte. 
3. The Master sends the second address byte. The Slave mode I
4. Software responds to the Slave Address Match interrupt by reading the I2CISTAT
5. The Master notifies the Acknowledge and sends a Restart instruction, followed by the
– Initialize the MODE field in the I
– Optionally set the
– Initialize the
– Set
– Program the Baud Rate High and Low Byte registers for the I
which clears the
The Slave mode I
SLA
acknowledges, indicating that it is available to accept the transaction.
the second address byte with the value in
the I2CISTAT register is set = 1, causing a Slave Address Match interrupt. The
is set = 0, indicating a write to the Slave. If a match occurs, the I
acknowledges on the I
register which clears the
first address byte with the R/W = 1. The Slave mode I
Restart followed by the first address byte with a match to
R/W = 1 (Master reads from Slave). The Slave I
W=0 A Slave Address
Master/Slave mode with 10-bit addressing.
I2CMODE register.
[9:8] and detects the R/W bit = 0 (write from Master to Slave). The I
displays the data transfer format for a Master reading data from a Slave with 10-
IEN
= 1,
2nd Byte
NAK
SLA
SPRS
2
C Controller recognizes the start of a 10-bit address with a match to
[7:0] bits in the I2CSLVAD register and
= 0 in the I
GCE
2
P R E L I M I N A R Y
bit.
C bus, indicating that it is available to accept the data.
SAM
bit.
A S Slave Address
bit. When the
2
C Control register.
2
2
C Master/Slave Controller operating as a Slave in
C Mode register for either Slave-only mode or
1st Byte
SLA
RD
[7:0]. If there is a match, the
bit = 0, no further action is required.
2
C Controller sets the
R=1
2
C Controller recognizes the
A
SLA
I
2
SLA
C Master/Slave Controller
Product Specification
2
Data
C Controller compares
[9:8] and detects the
ZNEO
2
[9:8] in the
2
C baud rate.
C Controller
A
SAM
2
Z16F Series
Data
C Controller
SAM
bit in the
RD
bit in
A P
bit
222