Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 329

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Table 166. On-Chip Debugger Commands
Debug Command
Read Revision
Read OCD Status Register
Read OCD Control Register
Write OCD Control Register
Read Registers (CPU registers R15-R0)
Write Registers (CPU registers R15-R0)
Read Program Counter
Write Program Counter
Read Flags
Write Instruction
Read Register (single CPU register)
Write Register (single CPU register)
•
The On-Chip Debugger commands are summarized in
Read Each Memory CRC — The Read memory CRC command computes and return
the CRC of a block each 4K memory block.
The
The
MemoryCRC
The
returned for each 4K block and is reset at the start of each block. The
field determines how many blocks of memory to compute the
DBG --> MemoryCRC[8:15]
DBG --> CRC[0:7]
DBG <-- {1111,BlockCount[3:0]}
DBG <-- BlockCount[11:4]
DBG <-- 00h
DBG <-- addr[23:16]
DBG <-- {addr[15:12],xxxx}
DBG ->> MemoryCRC[0:7]
DBG ->> MemoryCRC[8:15]
DBG --> CRC[0:7]
MemoryCRC
BlockCount
MemoryCRC
on.
is computed on memory in increments of 4K blocks. 
is computed on memory in increments of 4K blocks. The CRC is
field determines how many blocks of memory to compute the
P R E L I M I N A R Y
0100-(regno[3:0])
0100-(regno[3:0])
Command Byte
0000-0000
0000-0001
0000-0010
0000-0100
0000-0101
0000-1000
0000-1001
0000-0011
0000-0110
0000-0111
Table
Cannot single step (bit0 has not
Disabled by Read Protect
166.
Product Specification
MemoryCRC
ZNEO
Option Bit
effect)
On-Chip Debugger
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
BlockCount
Z16F Series
on.
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