PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 98

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
7.6.2
Figure 7-2 shows an example of 16-bit Word Write
mode for PIC18F65J10 devices. This mode is used for
word-wide memories which include some of the
EPROM and Flash-type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
DS39663D-page 96
Note 1:
a
16-BIT WORD WRITE MODE
PIC18F8XJ10
TBLWT
2:
A<19:16>
AD<15:8>
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
AD<7:0>
cycle
16-BIT WORD WRITE MODE EXAMPLE
WRH
ALE
CE
OE
(1)
to
an
even
address
Preliminary
373
373
During
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
A<20:1>
D<15:0>
a
TBLWT
Address Bus
Data Bus
Control Lines
D<15:0>
A<x:0>
cycle
© 2006 Microchip Technology Inc.
CE
EPROM Memory
to
OE
JEDEC Word
an
WR
odd
(2)
address