PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 70

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 5-3 and Table 5-4.
TABLE 5-3:
DS39663D-page 68
Address
Note 1:
FEDh POSTDEC0
FECh
FFDh
FFCh
FEEh POSTINC0
FEBh
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
2:
3:
PREINC0
PREINC1
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices.
SPECIAL FUNCTION REGISTERS
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
TOSU
TOSH
Name
TOSL
BSR
PCL
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J10 FAMILY DEVICES
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDFh
FDEh POSTINC2
FDBh
FDAh
FCEh
FCBh
FCAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
SSP1STAT
SSP1ADD
WDTCON
SSP1BUF
OSCCON
ADRESH
ADCON0
ADCON1
ADCON2
ADRESL
INDF2
STATUS
TMR0H
T0CON
TMR1H
T2CON
FSR2H
TMR0L
TMR1L
T1CON
FSR2L
RCON
Name
TMR2
—
—
PR2
(2)
(2)
(1)
(1)
(1)
(1)
(1)
Address
Preliminary
FBDh
FBCh
FBFh
FBEh
FBBh
FBAh
FAEh
FADh
FACh
FABh
FAAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CCP1CON
CCP2CON
CCP3CON
ECCP1AS
CVRCON
PSPCON
RCREG1
CCPR1H
CCPR2H
CCPR3H
SPBRG1
TXREG1
EECON2
EECON1
CCPR1L
CCPR2L
CCPR3L
RCSTA1
CMCON
TXSTA1
TMR3H
T3CON
TMR3L
Name
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
—
—
—
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
(2)
(2)
(2)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
MEMCON
OSCTUNE
PORTH
PORTJ
TRISH
TRISJ
PORTG
LATH
PORTF
PORTE
PORTD
PORTC
PORTB
LATJ
PORTA
TRISG
TRISD
TRISC
TRISB
TRISA
TRISF
TRISE
Name
LATG
LATC
LATF
LATE
LATD
LATB
LATA
IPR1
PIR1
PIE1
© 2006 Microchip Technology Inc.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Address
F7Dh
F7Ch BAUDCON2
F6Dh
F6Ch
F7Eh BAUDCON1
F7Bh
F7Ah
F6Eh
F6Bh
F6Ah
F7Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
ECCP1DEL
ECCP3DEL
ECCP2DEL
SSP2CON1
SSP2CON2
SSP2STAT
SPBRGH1
SPBRGH2
CCP4CON
CCP5CON
ECCP3AS
ECCP2AS
SSP2ADD
SSP2BUF
RCREG2
CCPR4H
CCPR5H
SPBRG2
TXREG2
CCPR4L
CCPR5L
RCSTA2
TXSTA2
T4CON
Name
TMR4
—
—
PR4
—
—
(2)
(2)
(2)
(2)