PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 89

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 64
times for each programming operation. All of the table
write operations will essentially be short writes because
only the holding registers are written. At the end of
updating the 64 holding registers, the EECON1 register
must be written to in order to start the programming
operation with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
6.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
© 2006 Microchip Technology Inc.
TBLPTR = xxxxx0
Read 1024 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the row erase procedure.
Load Table Pointer register with address of first
byte being written, minus 1.
Write the 64 bytes into the holding registers with
auto-increment.
Set the WREN bit (EECON1<2>) to enable byte
writes.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
TABLE WRITES TO FLASH PROGRAM MEMORY
8
TBLPTR = xxxxx1
Holding Register
8
Preliminary
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for T
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
15. Verify the memory (table read).
An example of the required code is shown in
Example 6-3 on the following page.
Note:
Holding Register
Note 1: Unlike
Disable interrupts.
Write 55h to EECON2.
(see parameter D133A).
are written to program memory.
2: To maintain the endurance of the program
8
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
members of the PIC18F87J10 family do
not reset the holding registers after a
write occurs. The holding registers must
be cleared or overwritten before a
programming sequence.
memory cells, each Flash byte should not
be programmed more than one time
between
attempting to modify the contents of the
target cell a second time, a row erase of
the target row, or a bulk erase of the entire
memory, must be performed.
PIC18F87J10
previous
erase
TBLPTR = xxxx3F
operations.
PICmicro
Holding Register
DS39663D-page 87
8
devices,
Before
IW