PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 40

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS to ‘11’. When the
clock source is switched to the INTRC (see Figure 3-3),
the primary oscillator is shut down and the OSTS bit is
cleared.
FIGURE 3-3:
FIGURE 3-4:
DS39663D-page 38
Peripheral
Program
Counter
INTRC
OSC1
Note 1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
INTRC
Output
OSC1
Clock
Q1
OST
SCS1:SCS0 Bits Changed
Q2
= 1024 T
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
PC
Q3
Q4
OSC
; T
Q1
Q1
PLL
T
1
= 2 ms (approx). These intervals are not shown to scale.
OST
(1)
PC
Q2
2
Clock Transition
3
T
PLL (1)
OSTS Bit Set
Q3
Preliminary
PC + 2
Q4
n-1
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2006 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
Q3
Q3