PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 395

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer2 .............................................................................. 157
Timer3 .............................................................................. 159
Timer4 .............................................................................. 163
Timing Diagrams
© 2006 Microchip Technology Inc.
Overflow Interrupt .................................................... 151
Resetting, Using the ECCP Special Event Trigger .. 154
Special Event Trigger (ECCP) ................................. 176
TMR1H Register ...................................................... 151
TMR1L Register ....................................................... 151
Use as a Clock Source ............................................ 153
Use as a Real-Time Clock ....................................... 154
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register ............................................................ 177
TMR2 to PR2 Match Interrupt .................................. 177
16-bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .......................................................... 159, 161
Overflow Interrupt ............................................ 159, 161
Special Event Trigger (ECCP) ................................. 161
TMR3H Register ...................................................... 159
TMR3L Register ....................................................... 159
Associated Registers ............................................... 164
MSSP Clock Shift ..................................................... 164
Operation ................................................................. 163
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................ 163
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 163
TMR4 to PR4 Match Interrupt .......................... 163, 164
A/D Conversion ........................................................ 376
Asynchronous Reception ......................................... 248
Asynchronous Transmission .................................... 246
Asynchronous Transmission (Back to Back) ........... 246
Automatic Baud Rate Calculation ............................ 244
Auto-Wake-up Bit (WUE) During Normal Operation 249
Auto-Wake-up Bit (WUE) During Sleep ................... 249
Baud Rate Generator with Clock Arbitration ............ 221
BRG Overflow Sequence ......................................... 244
BRG Reset Due to SDAx Arbitration During Start Condi-
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Repeated Start Condition (Case
Bus Collision During a Start Condition (SCLx = 0) .. 230
Bus Collision During a Stop Condition (Case 1) ...... 232
Bus Collision During a Stop Condition (Case 2) ...... 232
Bus Collision During Start Condition (SDAx Only) ... 229
Bus Collision for Transmit and Acknowledge ........... 228
Capture/Compare/PWM (Including ECCP Modules) 366
CLKO and I/O .......................................................... 361
Clock Synchronization ............................................. 214
Clock/Instruction Cycle .............................................. 62
EUSART Synchronous Receive (Master/Slave) ...... 375
EUSART Synchronous Transmission (Master/Slave) ....
Example SPI Master Mode (CKE = 0) ..................... 367
Example SPI Master Mode (CKE = 1) ..................... 368
Example SPI Slave Mode (CKE = 0) ....................... 369
Example SPI Slave Mode (CKE = 1) ....................... 370
External Clock (All Modes Except PLL) ................... 359
tion ................................................................... 230
1) ...................................................................... 231
2) ...................................................................... 231
375
Preliminary
External Memory Bus for Sleep (Extended Microcontrol-
External Memory Bus for TBLRD (Extended Microcon-
Fail-Safe Clock Monitor ........................................... 287
First Start Bit Timing ................................................ 222
Full-Bridge PWM Output .......................................... 181
Half-Bridge PWM Output ......................................... 180
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 146
Parallel Slave Port (PSP) Write ............................... 145
Program Memory Read ........................................... 362
Program Memory Write ........................................... 363
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
PWM Direction Change ........................................... 183
PWM Direction Change at Near 100% Duty Cycle .. 183
PWM Output ............................................................ 170
Repeated Start Condition ........................................ 223
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 250
Slave Synchronization ............................................. 195
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 194
SPI Mode (Slave Mode, CKE = 0) ........................... 196
SPI Mode (Slave Mode, CKE = 1) ........................... 196
Synchronous Reception (Master Mode, SREN) ...... 253
Synchronous Transmission ..................................... 251
Synchronous Transmission (Through TXEN) .......... 252
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 365
Transition for Entry to Idle Mode ............................... 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake from Idle to Run Mode ............... 40
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence .................................... 227
C Bus Data ............................................................ 371
C Bus Start/Stop Bits ............................................ 371
C Master Mode (7 or 10-bit Transmission) ........... 225
C Master Mode (7-bit Reception) .......................... 226
C Slave Mode (10-bit Reception, SEN = 0) .......... 211
C Slave Mode (10-bit Reception, SEN = 0, ADMSK =
C Slave Mode (10-bit Reception, SEN = 1) .......... 216
C Slave Mode (10-bit Transmission) ..................... 212
C Slave Mode (7-bit Reception, SEN = 0) ............ 207
C Slave Mode (7-bit Reception, SEN = 0, ADMSK =
C Slave Mode (7-bit Reception, SEN = 1) ............ 215
C Slave Mode (7-bit Transmission) ....................... 209
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ........ 227
ler Mode) ................................................... 98, 100
troller Mode) .............................................. 98, 100
01001) ............................................................. 210
01011) ............................................................. 208
10-bit Address Mode) ...................................... 217
abled) .............................................................. 186
abled) .............................................................. 186
(OST) and Power-up Timer (PWRT) ............... 364
V
V
V
285
........................................................................... 47
DD
DD
DD
), Case 1 ..................................................... 46
), Case 2 ..................................................... 47
Rise < T
2
2
C Bus Data ....................................... 373
C Bus Start/Stop Bits ........................ 373
PIC18F87J10
PWRT
) ............................................ 46
DD
DS39663D-page 393
, V
DD
Rise > T
PWRT
DD
)
,