PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 255

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 19-13:
TABLE 19-8:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
RC6/TX1/CK1 pin
RC6/TX1/CK1 pin
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2
Name
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
RC7/RX1/DT1
(SCKP = 0)
(SCKP = 1)
(Interrupt)
(RG1/TX2/CK2 and RG2/RX2/DT2).
RC1IF bit
CREN bit
RCREG1
bit SREN
SREN bit
Write to
EUSART SYNCHRONOUS
MASTER RECEPTION
Read
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
pin
SSP2IF
SSP2IE
SSP2IP
Q2
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 0
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
CREN
SYNC
TX1IF
TX2IF
SCKP
Bit 4
Preliminary
bit 2
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
bit 3
RBIE
Bit 3
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE bits
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCxIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
bit CREN.
in the INTCON register (INTCON<7:6>) are set.
bit 4
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
CCP1IF
CCP5IF
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IP
TMR2IF
CCP4IF
CCP4IE
CCP4IP
INT0IF
OERR
TRMT
WUE
Bit 1
PIC18F87J10
bit 6
TMR1IF
TMR1IE
TMR1IP
CCP3IF
CCP3IE
CCP3IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 7
DS39663D-page 253
Reset Values
on page
Q1 Q2 Q3 Q4
49
51
51
51
51
51
51
51
51
51
52
52
52
‘0’