PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet
PIC18F67J10-I/PT
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PIC18F67J10-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F87J10 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS39663D ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Internal 31 kHz oscillator • Secondary oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops © 2006 Microchip Technology Inc. PIC18F87J10 FAMILY Peripheral Highlights: • High-current sink/source 25 mA/25 mA (PORTB and PORTC) • ...
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... Program Memory SRAM Data Device Flash # Single-Word (bytes) Instructions PIC18F65J10 32K 16384 PIC18F65J15 48K 24576 PIC18F66J10 64K 32768 PIC18F66J15 96K 49152 PIC18F67J10 128K 65536 PIC18F85J10 32K 16384 PIC18F85J15 48K 24576 PIC18F86J10 64K 32768 PIC18F86J15 96K 49152 PIC18F87J10 128K 65536 Pin Diagrams ...
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... RH7/AN15/P1B 19 (2) RH6/AN14/P1C 20 Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. © 2006 Microchip Technology Inc. PIC18F87J10 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39663D-page 4 Preliminary © 2006 Microchip Technology Inc. ...
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... PIC18F85J15 • PIC18F66J10 • PIC18F86J10 • PIC18F66J15 • PIC18F86J15 • PIC18F67J10 • PIC18F87J10 This family introduces a new line of low-voltage devices with the main traditional advantage of all PIC18 micro- controllers – namely, high computational performance and a rich feature set – extremely competitive price point ...
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... All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. Preliminary © 2006 Microchip Technology Inc. devices to (2048 bytes for ...
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... MSSP (2), Enhanced USART (2) Yes 15 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set enabled 80-pin TQFP Preliminary PIC18F87J10 PIC18F66J15 PIC18F67J10 DC – 40 MHz DC – 40 MHz 96K 128K 49152 65536 3936 3936 DC – 40 MHz DC – ...
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... Reset ALU<8> Timer (2) Reset SS MCLR Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART2 EUSART1 Preliminary PORTA (1) RA0:RA5 12 PORTB (1) RB0:RB7 4 Access Bank 12 PORTC (1) RC0:RC7 PORTD (1) RD0:RD7 8 PRODL PORTE (1) RE0:RE7 PORTF 8 (1) RF1:RF7 8 PORTG (1) RG0:RG4 Comparators MSSP1 MSSP2 © 2006 Microchip Technology Inc. ...
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... ADC Timer0 10-bit ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2006 Microchip Technology Inc. Data Latch 8 8 Data Memory (2.0, 3.9 PCLATH Kbytes) PCLATU Address Latch ...
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... Analog input 3. I Analog A/D reference voltage (high) input. I/O ST Digital I/ Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C™ mode © 2006 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. ...
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... ECCP1 PWM output C. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O ST Capture 2 input/Compare 2 output/PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit CCP2MX is cleared. © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2006 Microchip Technology Inc. Pin Buffer Type Type I ST Master Clear (Reset) input ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Slave Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description 2 C mode © 2006 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog input 10. O — Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... Digital I/O. I Analog Analog input 14. O — ECCP1 PWM output C. I/O ST Digital I/O. I Analog Analog input 15. O — ECCP1 PWM output B. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD © 2006 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set). 3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2006 Microchip Technology Inc. Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J10 NOTES: DS39663D-page 26 Preliminary © 2006 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2006 Microchip Technology Inc. FIGURE 2-1: ( Output (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... OSC2 is not available. FIGURE 2-3: Clock from of external Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F87J10 /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F87J10 (HS Mode) Open OSC2 © 2006 Microchip Technology Inc. ...
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... Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. FIGURE 2-4: HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 OSC1 ...
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... Features of the CPU” for Configuration register details. PIC18F87J10 Family HS, EC HSPLL, ECPLL 4 x PLL T1OSC Internal Oscillator INTRC Source FOSC2:FOSC0 Preliminary © 2006 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2006 Microchip Technology Inc. PIC18F87J10 2.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device’ ...
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... MSSP slave, PSP, INTn pins and others). Peripherals that may add significant current Section 26.2 “DC Characteristics: Power-Down and Supply Current”. Preliminary (1) U-0 R/W-0 R/W-0 — SCS1 SCS0 bit Writable bit consumption are listed © 2006 Microchip Technology Inc. in ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2006 Microchip Technology Inc. PIC18F87J10 The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes) ...
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... PIC18F87J10 NOTES: DS39663D-page 34 Preliminary © 2006 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2006 Microchip Technology Inc. PIC18F87J10 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC2:FOSC0 Configuration bits • ...
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... SEC_RUN mode is entered by setting the SCS1:SCS0 bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Preliminary © 2006 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL © 2006 Microchip Technology Inc. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) PLL ( n-1 n Clock Transition OSTS Bit Set Preliminary © 2006 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2006 Microchip Technology Inc. 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2006 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2006 Microchip Technology Inc. PIC18F87J10 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J10 NOTES: DS39663D-page 42 Preliminary © 2006 Microchip Technology Inc. ...
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... INTRC 11-bit Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. © 2006 Microchip Technology Inc. PIC18F87J10 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1) ...
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... POR was set to ‘1’ by software immediately after POR). DS39663D-page 44 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2006 Microchip Technology Inc. FIGURE 4- Note 1: External Power-on Reset circuit is required only if the V ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 4-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel. T PWRT T PWRT Preliminary © 2006 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 ...
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... FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc. T PWRT , V RISE > 3. PWRT Preliminary PIC18F87J10 ): CASE 2 DD ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2006 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F87J10 NOTES: DS39663D-page 54 Preliminary © 2006 Microchip Technology Inc. ...
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... Unimplemented Read as ‘0’ Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2006 Microchip Technology Inc. 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F87J10 FAMILY DEVICES Program Device Memory (Kbytes) PIC18F65J10 PIC18F85J10 PIC18F65J15 PIC18F85J15 PIC18F66J10 PIC18F86J10 PIC18F66J15 PIC18F86J15 PIC18F67J10 128 PIC18F87J10 Preliminary © 2006 Microchip Technology Inc. CONFIG1 through Configuration Word Addresses 32 7FF8h to 7FFFh 48 BFF8h to BFFFh 64 FFF8h to FFFFh ...
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... Unimplemented: Read as ‘0’ Legend Readable bit -n = Value after erase © 2006 Microchip Technology Inc. • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory; above this, the device accesses external program memory up to the 2-Mbyte program space limit ...
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... Yes Yes Preliminary (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes © 2006 Microchip Technology Inc. ...
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... TOSL 00h 1Ah 34h © 2006 Microchip Technology Inc. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... TOS value. R/C-0 U-0 R/W-0 R/W-0 (1) — SP4 SP3 (1) ( Writable bit U = Unimplemented ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 SP2 SP1 SP0 bit Clearable only bit x = Bit is unknown © 2006 Microchip Technology Inc. ...
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... WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2006 Microchip Technology Inc. PIC18F87J10 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2006 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2006 Microchip Technology Inc. The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary © 2006 Microchip Technology Inc. ...
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... Bank 6 FFh 00h = 0111 Bank 7 FFh 00h = 1000 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2006 Microchip Technology Inc. Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR 3FFh 400h ...
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... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2006 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2006 Microchip Technology Inc. Data Memory 000h 7 00h ...
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... LATC F6Bh RCSTA2 LATB F6Ah ECCP3AS LATA F69h ECCP3DEL (3) PORTJ F68h ECCP2AS (3) PORTH F67h ECCP2DEL PORTG F66h SSP2BUF PORTF F65h SSP2ADD PORTE F64h SSP2STAT PORTD F63h SSP2CON1 PORTC F62h SSP2CON2 (2) PORTB F61h — (2) PORTA F60h — © 2006 Microchip Technology Inc. ...
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... The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — ...
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... PSS1BD0 51, 185 0000 0000 CVR0 51, 273 0000 0000 CM0 51, 267 0000 0111 51, 161 xxxx xxxx 51, 161 xxxx xxxx TMR3ON 51, 159 0000 0000 — 51, 145 0000 ---- 51, 239 0000 0000 51, 247, 0000 0000 248 © 2006 Microchip Technology Inc. ...
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... The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’. 5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2006 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 SYNC ...
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... P3DC0 53, 184 0000 0000 PSS2BD0 53, 185 0000 0000 P2DC0 53, 184 0000 0000 53, 199, xxxx xxxx 233 53, 199 0000 0000 BF 53, 190, 0000 0000 200 SSPM0 53, 191, 0000 0000 201 SEN 53, 202 0000 0000 © 2006 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the ...
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... HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2006 Microchip Technology Inc. other Stack Pointer ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2006 Microchip Technology Inc. the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... Indirect Addressing. Similarly, operations by Indirect Addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. Preliminary © 2006 Microchip Technology Inc. ...
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... Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. © 2006 Microchip Technology Inc. PIC18F87J10 When using the extended instruction set, this addressing mode requires the following: • ...
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... F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory Preliminary © 2006 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2006 Microchip Technology Inc. Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J10 NOTES: DS39663D-page 80 Preliminary © 2006 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F87J10 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Preliminary Table Latch (8-bit) TABLAT © 2006 Microchip Technology Inc. ...
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... The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-x — — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> Preliminary TBLPTRL 0 © 2006 Microchip Technology Inc. ...
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... TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2006 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2006 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2006 Microchip Technology Inc. The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block Preliminary © 2006 Microchip Technology Inc. ...
Page 91
... EECON2 Program Memory Control Register 2 (not a physical register) EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. © 2006 Microchip Technology Inc. 6.6 Flash Program Operation During Code Protection See Section 23.6 “Program Verification and Code Protection” ...
Page 92
... PIC18F87J10 NOTES: DS39663D-page 90 Preliminary © 2006 Microchip Technology Inc. ...
Page 93
... For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2006 Microchip Technology Inc. The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 94
... Data Width mode is selected. U-0 R/W-0 R/W-0 U-0 — WAIT1 WAIT0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-0 — WM1 WM0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 95
... Microchip Technology Inc. 7.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
Page 96
... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. Preliminary © 2006 Microchip Technology Inc. are affected; A19:A16 the MEMCON ...
Page 97
... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2006 Microchip Technology Inc. PIC18F87J10 During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus ...
Page 98
... A<20:1> 373 D<15:0> 373 Preliminary cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2006 Microchip Technology Inc. ...
Page 99
... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2006 Microchip Technology Inc. PIC18F87J10 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 100
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2006 Microchip Technology Inc. ...
Page 101
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2006 Microchip Technology Inc. PIC18F87J10 will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 102
... TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 55h ABh 0Eh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2006 Microchip Technology Inc. ...
Page 103
... If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2006 Microchip Technology Inc. PIC18F87J10 In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
Page 104
... PIC18F87J10 NOTES: DS39663D-page 102 Preliminary © 2006 Microchip Technology Inc. ...
Page 105
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F87J10 EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 106
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2006 Microchip Technology Inc. ...
Page 107
... Individual interrupts can be disabled through their corresponding enable bits. © 2006 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro Compatibility mode, the interrupt priority bits for each source have no effect. INTCON< ...
Page 108
... PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary © 2006 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 109
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 110
... DS39663D-page 108 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 111
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F87J10 R/W-0 R/W-0 ...
Page 112
... R-0 R-0 R/W-0 R/W-0 RC1IF TX1IF SSP1IF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 113
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 U-0 U-0 R/W-0 U-0 — — BCL1IF — ...
Page 114
... R = Readable bit -n = Value at POR DS39663D-page 112 R-0 R-0 R/W-0 R/W-0 RC2IF TX2IF TMR4IF CCP5IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 115
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 116
... R = Readable bit -n = Value at POR DS39663D-page 114 U-0 U-0 R/W-0 U-0 — — BCL1IE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 117
... CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 R-0 R-0 R/W-0 R/W-0 RC2IE TX2IE TMR4IE CCP5IE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 118
... R = Readable bit -n = Value at POR DS39663D-page 116 R/W-1 R/W-1 R/W-1 R/W-1 RC1IP TX1IP SSP1IP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 119
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 U-0 U-0 R/W-1 U-0 — — BCL1IP — Writable bit U = Unimplemented bit, read as ‘ ...
Page 120
... R = Readable bit -n = Value at POR DS39663D-page 118 R/W-1 R/W-1 R/W-1 R/W-1 RC2IP TX2IP TMR4IP CCP5IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 121
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 R-1 — — RI ...
Page 122
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 00h) will set flag bit, TMR0IF. In © 2006 Microchip Technology Inc. ...
Page 123
... Port Note 1: I/O pins have diode protection to V © 2006 Microchip Technology Inc. 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 124
... MOVWF TRISA Preliminary + and REF INITIALIZING PORTA ; Initialize PORTA by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Configure A/D ; Configure comparators ; for digital input ; Value used to ; initialize data ; direction ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2006 Microchip Technology Inc. ...
Page 125
... TRISA — — ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input enabled. ...
Page 126
... Extended Microcontroller mode. If the device is in Microcontroller mode, the alternate assignment for ECCP2 is RE7. As with other ECCP2 configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. Preliminary © 2006 Microchip Technology Inc. wake the device from ...
Page 127
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD are enabled. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATB< ...
Page 128
... RB4 RB3 RB2 LATB5 LATB4 LATB3 LATB2 TRISB5 TRISB4 TRISB3 TRISB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 52 LATB1 LATB0 52 TRISB1 TRISB0 52 INT0IF RBIF 49 INT3IP RBIP 49 INT2IF INT1IF 49 © 2006 Microchip Technology Inc. ...
Page 129
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2006 Microchip Technology Inc. PIC18F87J10 Note: These pins are configured as digital inputs on any device Reset ...
Page 130
... LATC<7> data output. ST PORTC<7> data input. ST Asynchronous serial receive data input (EUSART1 module). DIG Synchronous serial data output (EUSART1 module); takes priority over port data. ST Synchronous serial data input (EUSART1 module). User must configure as an input. Preliminary © 2006 Microchip Technology Inc. ...
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... TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATBC6 TRISC TRISC7 TRISC6 © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary ...
Page 132
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2006 Microchip Technology Inc. ...
Page 133
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Available on 80-pin devices only. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATD< ...
Page 134
... Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD5 TRISD4 TRISD3 TRISD2 (1) RJPU RG4 RG3 RG2 Preliminary Description (1) (1) (1) (1) Reset Bit 1 Bit 0 Values on page RD1 RD0 52 LATD1 LATD0 52 TRISD1 TRISD0 52 RG1 RG0 52 © 2006 Microchip Technology Inc. ...
Page 135
... REPU (PORTG<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. © 2006 Microchip Technology Inc. PIC18F87J10 PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
Page 136
... External memory interface, data bit 13 input. O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Preliminary Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) © 2006 Microchip Technology Inc. ...
Page 137
... LATE LATE7 LATE6 TRISE TRISE7 TRISE6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATE<6> data output PORTE<6> data input. O DIG External memory interface, address/data bit 14 output. ...
Page 138
... MOVLW 07h ; MOVWF CMCON ; Turn off comparators MOVLW 0Fh; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0CEh ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF1 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs Preliminary © 2006 Microchip Technology Inc. ...
Page 139
... CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATF<1> data output; not affected by analog input PORTF<1> data input; disabled when analog input enabled. ...
Page 140
... EXAMPLE 10-7: INITIALIZING PORTG CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method ; to clear output ; data latches MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs Preliminary © 2006 Microchip Technology Inc. ...
Page 141
... REPU LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2006 Microchip Technology Inc. I/O Type O DIG LATG<0> data output PORTG<0> data input. O DIG CCP3 Compare and PWM output ...
Page 142
... CLRF LATH ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Configure PORTH as MOVWF ADCON1 ; digital I/O MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs Preliminary © 2006 Microchip Technology Inc. ...
Page 143
... Name Bit 7 Bit 6 PORTH RH7 RH6 LATH LATH7 LATH6 TRISH TRISH7 TRISH6 © 2006 Microchip Technology Inc. I/O Type DIG LATH<0> data output. ST PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ST PORTH< ...
Page 144
... EXAMPLE 10-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTG by ; clearing output ; data latches CLRF LATJ ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs Preliminary © 2006 Microchip Technology Inc. ...
Page 145
... RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 TRISJ5 PORTG RDPU REPU Legend: Shaded cells are not used by PORTJ. © 2006 Microchip Technology Inc. I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
Page 146
... CK or PORTD Data Latch PORTD EN EN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes to V Preliminary © 2006 Microchip Technology Inc. RDx pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and ...
Page 147
... R = Readable bit -n = Value at POR FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF © 2006 Microchip Technology Inc. R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Q3 ...
Page 148
... TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 52 LATD1 LATD0 52 TRISD1 TRISD0 52 RE1 RE0 52 LATE1 LATE0 52 TRISE1 TRISE0 52 — — — 51 INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 © 2006 Microchip Technology Inc. ...
Page 149
... Prescale value Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 150
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...
Page 151
... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. ...
Page 152
... PIC18F87J10 NOTES: DS39663D-page 150 Preliminary © 2006 Microchip Technology Inc. ...
Page 153
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 154
... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...
Page 155
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F87J10 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 156
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary © 2006 Microchip Technology Inc. ...
Page 157
... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
Page 158
... PIC18F87J10 NOTES: DS39663D-page 156 Preliminary © 2006 Microchip Technology Inc. ...
Page 159
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 160
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP © 2006 Microchip Technology Inc. ...
Page 161
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the CCP and ECCP modules ...
Page 162
... RC1/T1OSI and 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...
Page 163
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2006 Microchip Technology Inc. 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 164
... PIC18F87J10 NOTES: DS39663D-page 162 Preliminary © 2006 Microchip Technology Inc. ...
Page 165
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
Page 166
... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Preliminary Set TMR4IF TMR4 Output (to PWM) PR4 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 CCP4IP CCP3IP 51 CCP4IF CCP3IF 51 CCP4IE CCP3IE © 2006 Microchip Technology Inc. ...
Page 167
... Reserved 11xx = PWM mode Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. register. For the sake of clarity, all CCP module opera- tion in the following sections is described with respect to CCP4, but is equally applicable to CCP5. Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules ...
Page 168
... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. timer are in © 2006 Microchip Technology Inc. ...
Page 169
... CCP4CON<3:0> Q1:Q4 CCP5CON<3:0> CCP5 pin Prescaler © 2006 Microchip Technology Inc. 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
Page 170
... Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. Set CCP4IF Compare Output Match Logic 4 CCP4CON<3:0> T3CCP2 Set CCP5IF Compare Output Match Logic 4 CCP5CON<3:0> Preliminary CCP4 pin TRIS Output Enable CCP5 pin TRIS Output Enable © 2006 Microchip Technology Inc. ...
Page 171
... Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — RI ...
Page 172
... CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) “Timer2 Module” and L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2006 Microchip Technology Inc. ...
Page 173
... PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2006 Microchip Technology Inc. 16.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 (PR4) register ...
Page 174
... CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 CCP4IF CCP3IF 51 CCP4IE CCP3IE 51 CCP4IP CCP3IP 51 TRISG1 TRISG0 © 2006 Microchip Technology Inc. ...
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... Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 The control register for the Enhanced CCP module is shown in Register 17-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality ...
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... Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 16.1.1 “CCP Resources”. Preliminary © 2006 Microchip Technology Inc. Modules and Timer ...
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... Compatible CCP ECCP2 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2006 Microchip Technology Inc. RC2 RE6 RE5 All PIC18F6XJ10/6XJ15 Devices: RE6 RE5 P1A ...
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... N/A N/A P3D N/A N/A RG3/CCP4 RH7/AN15 RH6/AN14 RG3/CCP4 P3B RH6/AN14 P3D P3B P3C RG3/CCP4 RH7/AN15 RH6/AN14 RG3/CCP4 RH5/AN13 RH4/AN12 RG3/CCP4 RH5/AN13 RH4/AN12 P3D RH5/AN13 RH4/AN12 CCP” mode as in Tables 17-1 for PWM Operation” or © 2006 Microchip Technology Inc. ...
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... PR2 Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2006 Microchip Technology Inc. waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle ( ...
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... The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 17-2. ) bits 9.77 kHz 39.06 kHz FFh FFh Preliminary 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2006 Microchip Technology Inc. ...
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... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”). © 2006 Microchip Technology Inc. PIC18F87J10 0 Duty Cycle Period (1) (1) Delay Delay 0 ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ PIC18F87J10 FET Driver P1A FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period Period td (1) ( Load + V - FET Driver FET Driver © 2006 Microchip Technology Inc. ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2006 Microchip Technology Inc. P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 17-1, Table 17-2 and Table 17-3. The corresponding TRIS bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2006 Microchip Technology Inc. ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2006 Microchip Technology Inc. (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC Forward Period ...
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... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary are selected using the bits (bits<6:4> of the PSS1AC1:PSS1AC0 and R/W-0 R/W-0 PxDC1 PxDC0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘ ...
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... PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary PWM Resumes ECCP1ASE Cleared by Firmware PWM Resumes © 2006 Microchip Technology Inc. ...
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... ECCPxAS2:ECCPxAS0 bits. • Select the shutdown states of the PWM output pins using PSSxAC1:PSSxAC0 and PSSxBD1:PSSxBD0 bits. • Set the ECCPxASE bit (ECCPxAS<7>). © 2006 Microchip Technology Inc auto-restart operation is required, set the PxRSEN bit (ECCPxDEL<7>). 9. Configure and start TMRn (TMR2 or TMR4): • ...
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... BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 — TMR3IF CCP2IF 51 — TMR3IE CCP2IE 51 — TMR3IP CCP2IP 51 CCP4IF CCP3IF 51 CCP4IE CCP3IE 51 CCP4IP CCP3IP 51 TRISB1 TRISB0 52 TRISC1 TRISC0 52 TRISE1 TRISE0 52 TRISG1 TRISG0 52 TRISH1 TRISH0 51, CCPxM0 51 51, 53 PxDC1 PxDC0 53 © 2006 Microchip Technology Inc. ...
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... SSP1CON1 SSP2CON1 control the same features for two different modules. © 2006 Microchip Technology Inc. PIC18F87J10 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes ...
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... A write to SSPxBUF will write to both SSPxBUF and SSPxSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary the SSPxBUF is not R-0 R-0 R-0 R bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...
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... Example 18-1 shows the loading of the SSPxBUF transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. Preliminary © 2006 Microchip Technology Inc. register completed (SSPxSR) for data ...
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... Shift Register (SSPxSR) LSb MSb PROCESSOR 1 © 2006 Microchip Technology Inc. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 18.3.4 TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers ...
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... SMP bit. The time when the SSPxBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 © 2006 Microchip Technology Inc. ...
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... Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF © 2006 Microchip Technology Inc. transmitted byte and becomes a floating output. Exter- nal pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the with (SSPxCON1<3:0> = 0100), module will reset if the SSx pin is set to V ...
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... SDIx (SMP = 0) bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS39663D-page 196 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary ) 0 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 © 2006 Microchip Technology Inc. ...
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... EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2006 Microchip Technology Inc. PIC18F87J10 18.3.10 BUS MODE COMPATIBILITY Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
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... TRISF3 TRISF2 SSPEN CKP SSPM3 SSPM2 D R/W Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 CCP4IF CCP3IF 51 CCP4IE CCP3IE 51 CCP4IP CCP3IP 51 TRISC1 TRISC0 52 TRISD1 TRISD0 52 TRISF1 — SSPM1 SSPM0 50 50 © 2006 Microchip Technology Inc. ...