PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 256

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
19.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
19.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 19-9:
DS39663D-page 254
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit, TXxIF, will now be
set.
If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous
Slave Mode
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
EUSARTx Transmit Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
SSP2IF
SSP2IE
SSP2IP
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
—
Preliminary
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
SCKP
Bit 4
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
CCP1IF
CCP5IF
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
CCP4IE
CCP4IP
CCP4IF
INT0IF
OERR
TRMT
WUE
Bit 1
© 2006 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
CCP3IF
CCP3IE
CCP3IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
on page
Values
Reset
49
51
51
51
51
51
51
51
51
51
52
52
52