PIC18F67J10-I/PT Microchip Technology, PIC18F67J10-I/PT Datasheet - Page 389

• Manufacturer Part Number: PIC18F67J10-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 2.7 V, 3.6 V
• Supply Voltage (min): 2 V, 2.7 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Development Support ...................................................... 339
Device Overview .................................................................. 5
Direct Addressing ............................................................... 75
E
ECCP
Effect on Standard PIC Instructions ................................. 336
Effects of Power-Managed Modes on Various Clock Sources
Electrical Characteristics .................................................. 343
Enhanced Capture/Compare/PWM (ECCP) .................... 173
Enhanced Universal Synchronous Asynchronous Receiver
ENVREG pin .................................................................... 284
Equations
Errata ................................................................................... 4
EUSART
Extended Instruction Set
© 2006 Microchip Technology Inc.
Details on Individual Family Members ......................... 6
Features (64-Pin Devices) ........................................... 7
Features (80-Pin Devices) ........................................... 7
Associated Registers ............................................... 188
Capture and Compare Modes .................................. 176
Enhanced PWM Mode ............................................. 177
Standard PWM Mode ............................................... 176
32
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and Program Memory Mode ...
ECCP2 Outputs and Program Memory Modes ........ 174
Outputs and Configuration ....................................... 174
Pin Configurations for ECCP1 ................................. 175
Pin Configurations for ECCP2 ................................. 175
Pin Configurations for ECCP3 ................................. 176
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 174
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 174
Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 262
A/D Minimum Charging Time ................................... 262
Asynchronous Mode ................................................ 245
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 239
Synchronous Master Mode ...................................... 251
Synchronous Slave Mode ........................................ 254
ADDFSR .................................................................. 332
174
12-bit Break Transmit and Receive ................. 250
Associated Registers, Receive ........................ 248
Associated Registers, Transmit ....................... 246
Auto-Wake-up on Sync Break ......................... 248
Receiver ........................................................... 247
Setting Up 9-bit Mode with Address Detect ..... 247
Transmitter ....................................................... 245
Operation in Power-Managed Mode ................ 239
Associated Registers ....................................... 240
Auto-Baud Rate Detect .................................... 243
Baud Rate Error, Calculating ........................... 240
Baud Rates, Asynchronous Modes ................. 241
High Baud Rate Select (BRGH Bit) ................. 239
Sampling .......................................................... 239
Associated Registers, Receive ........................ 253
Associated Registers, Transmit ....................... 252
Reception ......................................................... 253
Transmission ................................................... 251
Associated Registers, Receive ........................ 255
Associated Registers, Transmit ....................... 254
Reception ......................................................... 255
Transmission ................................................... 254
Preliminary
External Clock Input (EC Modes) ...................................... 28
External Memory Bus ........................................................ 91
F
Fail-Safe Clock Monitor ........................................... 277, 286
Fast Register Stack ........................................................... 61
Firmware Instructions ...................................................... 289
Flash Configuration Words .............................................. 277
Flash Program Memory ..................................................... 81
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 310
H
Hardware Multiplier .......................................................... 103
ADDULNK ............................................................... 332
CALLW .................................................................... 333
MOVSF .................................................................... 333
MOVSS .................................................................... 334
PUSHL ..................................................................... 334
SUBFSR .................................................................. 335
SUBULNK ................................................................ 335
16-bit Byte Select Mode ............................................ 97
16-bit Byte Write Mode .............................................. 95
16-bit Data Width Modes ........................................... 94
16-bit Mode Timing .................................................... 98
16-bit Word Write Mode ............................................. 96
8-bit Mode .................................................................. 99
8-bit Mode Timing .................................................... 100
Address and Data Line Usage (table) ....................... 93
Address and Data Width ............................................ 93
Address Shifting ........................................................ 93
Control ....................................................................... 92
I/O Port Functions ...................................................... 91
Operation in Power-Managed Modes ...................... 101
Program Memory Modes ........................................... 94
Wait States ................................................................ 94
Weak Pull-ups on Port Pins ....................................... 94
Interrupts in Power-Managed Modes ...................... 287
POR or Wake-up from Sleep ................................... 287
WDT During Oscillator Failure ................................. 286
Associated Registers ................................................. 89
Control Registers ....................................................... 82
Erase Sequence ........................................................ 86
Erasing ...................................................................... 86
Operation During Code-Protect ................................. 89
Reading ..................................................................... 85
Table Pointer
Table Pointer Boundaries .......................................... 84
Table Reads and Table Writes .................................. 81
Write Sequence ......................................................... 87
Writing ....................................................................... 87
Introduction .............................................................. 103
Operation ................................................................. 103
Performance Comparison ........................................ 103
Extended Microcontroller ................................... 94
Microcontroller ................................................... 94
EECON1 and EECON2 ..................................... 82
TABLAT (Table Latch) Register ........................ 84
TBLPTR (Table Pointer) Register ...................... 84
Boundaries Based on Operation ....................... 84
Unexpected Termination ................................... 89
Write Verify ........................................................ 89
PIC18F87J10
DS39663D-page 387