DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 73

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
5.8.3
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x0000.
5.8.4
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT1
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT1
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
Freescale Semiconductor
BDFR is writable only through serial background debug commands, not from user programs.
Reset
Reset
BDFR
Field
0
W
W
R
R
System Background Debug Force Reset Register (SBDFR)
System Options Register (SOPT1)
COPE
Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be
written from a user program.
0
0
1
7
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
= Unimplemented or Reserved
COPT
0
0
1
6
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 5-5. System Options Register (SOPT1)
Table 5-5. SBDFR Field Descriptions
STOPE
0
0
0
5
5
0
0
1
4
4
Description
Chapter 5 Resets, Interrupts, and System Configuration
3
0
0
3
0
0
0
0
0
0
2
2
BKGDPE
0
0
1
1
1
RSTPE
BDFR
0
0
1
0
0
1
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