DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 56

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory
4.6
The FLASH module consists of high-page including nonvolatile registers that are copied into
corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH
memory. Refer to
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
4.6.1
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
Table 4-7
56
Reset
PRDIV8
DIV[5:0]
DIVLD
Field
7
6
5
W
R
FLASH Registers and Control Bits
shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
FLASH Clock Divider Register (FCDIV)
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 μs
to 6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
DIV5:DIV0 for selected bus frequencies.
0
7
Table 4-3
= Unimplemented or Reserved
PRDIV8
if PRDIV8 = 1 — f
if PRDIV8 = 0 — f
0
6
Figure 4-5. FLASH Clock Divider Register (FCDIV)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
and
Equation 4-1
Table 4-4
Table 4-6. FCDIV Field Descriptions
DIV5
0
5
FCLK
FCLK
for the absolute address assignments for all FLASH registers.
and
= f
Equation
= f
Bus
DIV4
Bus
0
4
÷ (8 × ([DIV5:DIV0] + 1))
Description
÷ ([DIV5:DIV0] + 1)
4-2.
Table 4-7
DIV3
3
0
shows the appropriate values for PRDIV8 and
DIV2
0
2
Freescale Semiconductor
DIV1
0
1
Eqn. 4-1
Eqn. 4-2
DIV0
0
0