DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 161

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5.2.3
Example 3 LCD setup requirements are reiterated in the table below:
Table 9-24
Freescale Semiconductor
LCDSUPPLY
FPENR[5:0]
XXXXXX10
1XXXXX00
0XXX0010
LCDCLKS
0X011X00
11100011
LCDBCTL
Example
Register
LCDCR1
LCDCR0
3
lists the required setup values required to initialize the LCD as specified by Example 3:
Operating
Voltage,
Initialization
VSUPPLY[1:0]
CPCADJ[1:0]
CLKADJ[5:0]
3.6-V
Bit/bit field
BRATE[2:0]
LCDCPMS
BLKMODE
LCDCPEN
HDRVBUF
V
DUTY[1:0]
BBYPASS
LCDSTP3
LCLK[2:0]
SOURCE
LPWAVE
FPENR0
FPENR1
FPENR2
FPENR3
FPENR4
FPENR5
LCDWAI
DD
DIV16
LCD Clock
18886 kHz
Source
Internal
Table 9-24. Initialization Register Values for Example 3
XXXXXXX0
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
11111111
11111111
11111111
11111111
11111111
100011
Binary
Value
011
010
Example 3
XX
00
11
X
X
X
X
1
1
1
1
0
0
LCD Glass
Operating
Voltage
5-V
Selects the bus clock as the LCD clock input
External clock reference = 0; Bus clock = 1
Adjusts the LCD clock input (see table 9-12)
Adjusts the LCD clock input (see table 9-12)
Enable the charge pump
Don’t care since power is from internal V
Doubler mode = 0; Tripler mode = 1
High drive buffer
Configure LCD charge pump clock source
Buffer Bypass; Buffer mode = 0; Unbuffered mode = 1
Power LCD via V
V
LCD is “off” in WAIT mode
LCD is “on” in STOP3 mode
For 1/4 duty cycle, select closest value to the desired 60 Hz LCD frame frequency
(see table 9-13). Note the LCD base frequency - 256.2 Hz
Low power waveform
For 160 segments (4x40), select 1/4 duty cycle (see table 9-11)
Blink individual segments; Blink Segments = 0; Blink All = 1
Using the LCD base frequency for the selected LCD frame frequency, select 2.0
Hz blink frequency (see table 9-15).
40 LCD frontplanes need to be enabled.
LL2
is generated from V
segments
Required
LCD
160
DD
internal power (see table 9-16). When VSUPPLY[1:0] = 00,
Frame
60 Hz Individual segment
Rate
LCD
DD .
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
Mode/Rate
Comment
Blinking
2.0 Hz
DD
WAIT modes
Behavior in
STOP3 and
STOP3: on
WAIT: off
LCD Power
Power via
Input
V
DD
161