TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 92

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

7.2 Divider Output (
7.2.1 Configuration
7.2.2 Control
Time Base Timer Control Register
buzzer drive. Divider output is from
Data output
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
(0036H)
TBTCR
fc/2
fc/2
fc/2
fc/2
13
12
11
10
The Divider Output is controlled by the Time Base Timer Control Register.
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
or fs/2
or fs/2
or fs/2
or fs/2
5
4
3
2
Divider output control register
DVOCK
DVOEN
(a) configuration
DVOEN
DVOCK
7
Output latch
A
B
C
D
D
MPX
2
S
Y
TBTCR
Q
6
DVO
Divider output
enable / disable
Divider Output (
frequency selection: [Hz]
DVOCK
DVOEN
)
5
DVO
Figure 7-3 Divider Output
DVO
(DV7CK)
)
pin.
4
(TBTEN)
Page 75
DVO pin
0: Disable
1: Enable
3
00
01
10
11
Port output latch
TBTCR<DVOEN>
DVO pin output
DV7CK = 0
2
NORMAL1/2, IDLE1/2 Mode
fc/2
fc/2
fc/2
fc/2
13
12
10
11
(TBTCK)
1
(b) Timing chart
DV7CK = 1
0
fs/2
fs/2
fs/2
fs/2
5
4
3
2
(Initial value: 0000 0000)
SLEEP1/2
SLOW1/2
TMP86PM49UG
Mode
fs/2
fs/2
fs/2
fs/2
5
4
3
2
R/W
R/W