TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 203

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

15.3 Function
SIO2SR<TXERR>
SIO2TDB
SIO2CR
<SIOINH>
SIO2CR<SIOS>
SIO2SR<SIOF>
SIO2SR<SEF>
SCK2
SO2 pin
SIO2SR<TXF>
INTSIO2
interrupt
request
15.3.3.2 Receive mode
pin
Writing transmit
data A
(1)
(2)
The receive mode is selected by writing “01B” to SIO2CR<SIOM>.
SIO2CR<SCK>. Transfer direction is selected by using SIO2CR<SIODIR>.
SCK2
the direction of the bit specified by SBI2DIR<SIODIR>.
clock falling edge.
rupt request is generated and SIO2SR<RXF> is set to “1”
when the all of the 8-bit data has been received. Automatic-wait function is released by reading a
received data from SIO2RDB. Then, receive operation is restarted after maximum 1-cycle of serial
clock.
SIO2RDB, before the next data shift-in operation is finished.
Starting the receive operation
Receive mode is selected by setting “01” to SIO2CR<SIOM>. Serial clock is selected by using
After SIO2CR<SIOS> is set to “1”, SIO2SR<SIOF> is set synchronously to “1” the falling edge of
Synchronizing with the
SIO2SR<SEF> is kept in high level, between the first clock falling edge of
When 8-bit data is received, the data is transferred to SIO2RDB from shift register. INTSIO2 inter-
Note: In internal clock operation, when the SIO2CR<SIOS> is set to "1", the serial clock is generated
During the receive operation
The SIO2SR<RXF> is cleared to “0” by reading a data from SIO2RDB.
In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function
In external clock operation, after SIO2SR<RXF> is set to “1”, the received data must be read from
Figure 15-9 Example of Transmit Error Processingme
A
pin.
from
A7 A6
Writing transmit
data B
SCK2
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
pin after maximum 1-cycle of serial clock frequency.
B
SCK2
pin's rising edge, the data is received sequentially from SI2 pin with
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Start shift
operation
Start shift
operation
SCK2
Unknown
TMP86PM49UG
pin and eighth