TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 206

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

15.3.3.3 Transmit/receive mode
SIO2CR<SIOS>
SIO2SR<SIOF>
SIO2SR<SEF>
SCK2
SI2 pin
SIO2SR<RXF>
SIO2SR<RXERR>
INTSIO2
interrupt
request
SIO2RDB
pin
(1)
The transmit/receive mode are selected by writing “10” to SIO2CR<SIOM>.
by using SIO2CR<SCK>. Transfer direction is selected by using SIO2CR<SIODIR>.
cleared to “0”.
SCK2
SIO2CR<SIODIR>, synchronizing with the
starts with the direction of the bit specified by SIO2CR<SIODIR>, synchronizing with the
pin's rising edge.
clock falling edge.
transferred to shift register. When 8-bit data has been received, the received data is transferred to
SIO2RDB from shift register, then the INTSIO2 interrupt request occurs, synchronizing with setting
SIO2SR<RXF> to “1”.
Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
Starting the transmit/receive operation
Transmit/receive mode is selected by writing “10B” to SIO2CR<SIOM>. Serial clock is selected
When a transmit data is written to the transmit buffer register (SIO2TDB), SIO2SR<TXF> is
After SIO2CR<SIOS> is set to “1”, SIO2SR<SIOF> is set synchronously to the falling edge of
The data is transferred sequentially starting from SO2 pin with the direction of the bit specified by
SIO2SR<SEF> is kept in high level between the first clock falling edge of
SIO2SR<TXF> is set to “1” at the rising edge of
Note 1: In internal clock operation, when the SIO2CR<SIOS> is set to "1", SIO2TDB is transferred to
Note 2: In external clock operation, when the falling edge is input from
Figure 15-12 Example of Receive Error Processing
pin.
shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
SCK2
set to "1", SIO2TDB is transferred to shift register immediately. When the rising edge is input
from
A7 A6
SCK2
pin.
Start shift
operation
pin, receive operation also starts.
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
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A
Start shift
operation
SCK2
Writing transmit
data A
SCK2
pin's falling edge. And receiving operation also
pin after the data written to the SIO2TDB is
B
Start shift
operation
Writing transmit
data B
SCK2
pin after SIO2CR<SIOS> is
Write a "0" after reading the
received data when a receive
error occurs.
SCK2
TMP86PM49UG
pin and eighth
SCK2