TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 222

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.6 Data Transfer of I
SCL pin
SDA pin
PIN
INTSBI
interrupt request
16.6.1 Device initialization
16.6.2 Start condition and slave address generation
16.6.3 1-word data transfer
bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA.
receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set “1” to the PIN, “10” to the SBIM, and “00”
to bits SWRST1 and SWRST0.
address and the direction bit which are set to the SBIDBR are output. The time from generating the START
condition until the falling SCL pin takes t
“0”. The SCL pin is pulled-down to the low level while the PIN is “0”. When an interrupt request occurs, the
TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from
the slave device.
whether the mode is a master or slave.
For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the data length to 8
Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an addressing format.
After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave
Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are
Confirm a bus free status (BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the SBIDBR.
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave
An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the
Note 2: The bus free must be confirmed by software within 98.0 µs (The shortest transmitting time according to the
Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine
Figure 16-9 Start Condition Generation and Slave Address Transfer
connected to a bus have initialized to and device does not generate a start condition. If not, the data can not
be received correctly because the other device starts transferring before an end of the initialization of a serial
bus interface circuit.
SBIDBR, data to been outputting may be destroyed.
I
"1" to the MST, TRX, BB, and PIN to generate the start conditions. If the writing of slave address and setting
of MST, TRX, BB and PIN doesn't finish within 98.0 µs, the other masters may start the transferring and the
slave address data written in SBIDBR may be broken.
2
C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set
Start condition
2
A6
C Bus
1
A5
2
A4
LOW
3
Slave address + Direction bit
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.
A3
4
A2
5
A1
6
A0
7
R/W
8
TMP86PM49UG
9
Acknowledge
signal from a
slave device