TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 220

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.5.9 Setting of I
16.5.10Arbitration lost detection monitor
SCL (Bus)
SDA pin (Master 1)
SDA pin (Master 2)
SDA (Bus)
time that the PIN is “0”, the SCL pin is pulled-down to low level.
the softrware.
face pins in a high level, and then, write “10” to SBIM. And switch a port mode after confirming that a bus is
free.
mented in order to guarantee the contents of transferred data.
neously on a bus. Master 1 and Master 2 output the same data until point “a”. After that, when Master 1 outputs
“1” and Master 2 outputs “0”, since the SDA line of a bus is wired AND, the SDA line is pulled-down to the
low level by Master 2. When the SCL line of a bus is pulled-up at point “b”, the slave device reads data on the
SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is
called “arbitration lost”. A master device which loses arbitration releases the SDA pin and the SCL pin in order
not to effect data transmitted from other masters with arbitration. When more than one master sends the same
data at the first word, arbitration occurs continuously after the second word.
the SCL line. If the levels are unmatched, arbitration is lost and the AL (Bit3 in SBISRB) is set to “1”.
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISRB) is cleared to “0”. During the
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes t
Although the PIN (Bit4 in SBICRB) can be set to “1” by the softrware, the PIN can not be cleared to “0” by
Note:When the arbitration lost occurs, if the slave address sent from the other master devices is not match, the
The SBIM (Bit3 and 2 in SBICRB) is used to set I
Set the SBIM to “10” in order to set I
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is imple-
Data on the SDA line is used for bus arbitration of the I
The following shows an example of a bus arbitration procedure when two master devices exist simulta-
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
• At the end of acknowledge signal when the received slave address matches to the value set by the
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
INTSBI interrupt request is generated. But the PIN is not cleared.
I2CAR
CALL”
2
C bus mode
Figure 16-7 Arbitration Lost
2
C bus mode. Before setting of I
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a
2
C bus mode.
b
2
C bus.
SDA pin becomes "1" after losing arbitration.
2
C bus mode, confirm serial bus inter-
LOW
.
TMP86PM49UG